I'm a Frontend VLSI Engineer with a strong foundation in both RTL Design and Design Verification.
I love turning hardware ideas into reality using HDL and validating them through robust verification techniques.
- 🔬 Specialized in RTL Design, FSMs, and Verification Methodologies
- 💻 Proficient in both hardware description
- 🧪 Passionate about functional simulation and design correctness
| Category | Tools / Skills |
|---|---|
| 💻 Languages | C, Python, Bash |
| ⚙️ HDLs | Verilog, SystemVerilog |
| 🔍 Verification | Testbenches, Assertions, Functional Simulation |
| 🧰 Tools | Vivado, ModelSim, VCS, GTKWave |
| ⚙️ Concepts | FSMs, RTL Design, Digital Logic, Verification |
📡 Published a research paper on wall-through imaging using mmWave radar in Springer at the 4th Conference on Computational Intelligence in Machine Learning (CIML).
|
|
|
|
|
|
- 📧 Email: [email protected]
- 💼 LinkedIn: muneessanid