hwtLib is the library of hardware components for hwt framework Any component can be exported as IP-exact IPcore using IpPackager or as Verilog/VHDL/SystemC code by to_rtl() (Verilog, VHDL, ...). Target language is specified by keyword parameter serializer. Note that for most of components there is a schematic in the documentation.

Majority of components in this library is actually configurable component generator. For example there is no address decoder which takes a list of addresses and produces a mapped register file for Axi4Lite interface. Instead there is a component AxiLiteEndpoint, which takes hdl type description of address space and generates a address decoders and convertors to other intefaces if requested. Another example is AxiS_frameParser, which takes a hdl type description of output data and can be also used to change alignment of a frame or split/cut frame as the type description can also contains unions, struct, streams, padding and other hdl data types.

Same applies to simulation. Instead of hardcoding address values in to testbench you should use a AddressSpaceProbe to discover a addresses of mapped memory cells and use this object to communicate through the bus interface, because you want to write a verification which does not depends on interface used nor manually compute addresses for each component variant.

• abstract - abstract classes for component classes like bus endpoint, etc
• amba - AXI interfaces and components for them (AXI3/4 DMAs, interconnects, Axi-stream components, Axi4Lite address decoders etc...)
• avalon - same thing as amba just for Avalon interfaces (AvalonST, AvalonMM, ... and components for them)
• cesnet - components and interfaces specific to Cesnet designs
• clocking - various generic PLLs, timer generators etc.
• examples - demonstrative examples of hwt functionality
• handshaked - components for handshaked interfaces (FIFO, AsyncFifo, Resizer, interconnects, Register, ...)
• img - image preprocessing utils (parse PNG font to bits for OLED, ...)
• interfaces - various interfaces which does not have it's package yet
• logic - various components like CRC generator, gray counter, decoders-encoders ...
• mem - various memories (BRAM, ROM, FIFO, Async FIFO, CAM, LUT, ...)
• peripheral - various peripheral interfaces and components for them (I2C, MDIO, SPI, UART, USB, Ethernet, ...)
• sim - simulation utils
• structManipulators - DMAs for specific data structures
• tests - tests which are not related to another components
• types - deffinitions of common types (uint32_t, ipv6_t, udp_t, ...)
• xilinx - components and interfaces specific to Xilinx based designs (IPIF, LocalLink, ...)

sudo pip3 install hwtLib

• analogdevicesinc/hdl/
• connectal - framework for software-driven hardware development
• corundum - Packet DMA
• enjoy-digital repositories - Migen, SoC level modules
• FPGAwars FPGA-peripherals - Verilog, simple peripherals
• leon/grlib - Library of SoC components
• myhdl-resources - MyHDL list of projects
• NyuziProcessor - GPGPU
• opencores
• openrisc - OpenRISC, FuseSoC, peripherals and cpu parts
• picorv32 - Verilog, A Size-Optimized RISC-V SoC
• PoC - VHDL, utils
• pulp-platform
• rhea - MyHDL, SoC level modules
• surf - VHDL, SoC/DSP/IO/Ethernet focused components
• tinyfpgax
• ultraembedded/cores - mostly Verilog, mostly peripherals
• ZipCPU repositories - Verilog, mostly peripherals, DSP