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AbhijeetJ-512/README.md

💫 About Me:

I am currently pursuing a Bachelor's in Electronics and Communication at KLE Technological University, with a deep focus on Digital VLSI and SoC Development. Passionate about processor design, memory architecture, and synthesis methodologies.

🔥 What I’m Working On

  • Building a RISC Processor 🏗️
  • Memory Design using Verilog 🔧
  • Synthesis and Analysis with Open-Source EDA Tools ⚙️

🛠️ Technical Skills

  • Hardware Description Languages: Verilog, VHDL
  • Synthesis & Verification: Yosys, iverilog, GTKWave
  • Programming: C, Python (for scripting & automation)
  • Version Control: Git, GitHub
  • Operating Systems: Linux, Windows

🎯 Areas of Interest

I am most interested in working on high-performance, low-power design methodologies, with a focus on digital SoC design and synthesis. I enjoy exploring processor architectures, memory design, and optimization techniques to push the limits of efficiency and performance.

🌱 Learning & Exploring

  • Open-Source EDA Tools for Advanced Synthesis 📡
  • High-Speed Memory & Bus Architectures 🚀
  • Low-Power Design Techniques 🔋

📊 GitHub Stats:



✍️ Random Dev Quote

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    A synthesizable Verilog implementation of a 2-way set-associative CPU cache featuring an efficient Least Recently Used (LRU) replacement policy. This project models realistic CPU-memory interaction…

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  3. I2C I2C Public

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  4. AXI2APB AXI2APB Public

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  5. FIFO FIFO Public

    RTL designs and simulations for FIFO buffers (Synchronous & Asynchronous) in Verilog, targeting robust data handling architectures.

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  6. Vedic-Multiplier Vedic-Multiplier Public

    This repository contains a Verilog implementation of a Vedic Multiplier, a high-speed and efficient multiplication technique based on Vedic mathematics (Urdhva Tiryakbhayam algorithm). It supports …

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