M.S. Electrical Engineering | B.S. Computer Engineering | RTL & Digital Design

[email protected]  |  LinkedIn  |  GitHub

I’m a Master’s student in Electrical Engineering at UTRGV with a B.S. in Computer Engineering. My work and interests focus on digital hardware design and RTL development, especially FPGA/ASIC design, computer architecture, and system-level integration.

I enjoy building practical hardware projects that reinforce strong fundamentals, ranging from CPU microarchitecture and pipelined datapaths to FSM-driven FPGA designs and real-time signal processing systems. I’m especially interested in designing digital systems that are clean, efficient, and scalable, with an emphasis on writing structured Verilog/SystemVerilog and developing designs that are easy to debug and verify.

Building a real-time FPGA DSP pipeline with autotune, reverb, and harmonic enhancement, using a Python-to-Verilog testbench (3.6M+ samples) and validating <15 ms latency on real trumpet recordings.

Designing a 32-bit, 5-stage pipelined RISC-V CPU with hazard detection and forwarding, expanding from a custom ISA simulator to Verilog RTL targeting FPGA implementation.

Implemented a 12-state Moore FSM with debounced inputs, clock division, and LED feedback on the Nexys A7-100T FPGA, fully verified with modular Verilog test sequences.

🧠 Graduate Teaching Assistant @ UTRGV (Spring 2026)
Managed 3 weekly Digital Systems Lab I sections supporting 100+ undergraduate students in core digital logic, breadboard prototyping, and debugging fundamentals.

🔬 Graduate Research Assistant @ UTRGV (Fall 2025)
Led semiconductor device research focused on Ga2O3 ultra wide bandgap devices, including thin-film deposition and electrical/material characterization.

🧑‍🏫 Teaching Assistant @ UTRGV (Summer 2025)
Supervised 3 weekly lab sessions covering analog circuits, instrumentation, and measurement. Provided hands-on troubleshooting support to improve lab efficiency and student outcomes.

🧪 Research Assistant @ UTRGV (Spring 2025)
Developed Federated Incremental Gaussian Process (F-IGP) algorithms with 1,000+ update cycles. Simulated 18,500+ samples across multi-agent networks, achieving a 72% reduction in NLL and a 48% reduction in MSE. Contributed as a co-author on a paper submitted to the Asilomar Conference on Signals, Systems, and Computers.

🧬 Undergraduate Researcher @ UTRGV (2024)
Led a 4-person team to build a real-time facial recognition system for classroom attentiveness using a custom CNN. Processed 4,000+ labeled samples, reaching 90%+ accuracy, and presented results to 200+ K-12 students.

🚗 NSF REU Research Intern (Summer 2023)
Collaborated in a 10-week research program focused on autonomous vehicle safety. Supported ML-based decision-making research aimed at reducing conflict zones by 50%.

📫 I’m always open to discussing digital hardware design, RTL/FPGA projects, and engineering opportunities.

Feel free to reach out at [email protected].