An open-source HDL register code generator fast enough to run in real time.

A tool to download Python packages for later offline installation on many platforms

VHDL compiler and simulator

VUnit is a unit testing framework for VHDL/SystemVerilog

Open Source Verification Bundle for VHDL and System Verilog

Live code in Pandoc Markdown

A simple Emacs minor mode for VUnit

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Issue handling for Evidence-based Software Engineering: based on the publicly available data

Lab exercises for Chisel in the digital electronics 2 course at DTU

VHDL related news.

GitHub-based statistics highlighting interesting facts about the HDL industry

VUnit GitHub action

SciPy library main repository

Interfacing VHDL and foreign languages with VUnit

Tests to evaluate the support of VHDL 2008 and VHDL 2019 features

A fast VHDL language server and analysis library written in Rust

A JSON library implemented in VHDL.

Develop the directors structure and testing infrastructure for CoreLib

A VHDL Core Library.

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

VHDL 2008/93/87 simulator

🌊 Digital timing diagram rendering engine