The Atalla x01 Project is a student-led initiative to design and implement a complete AI Hardware-Software stack -- from RTL to PyTorch integration. This project aims to become an open, reproducible, and research-grade infrastructure that unites all key accelerator components under one roof.

/docs/ -> Documentation of Arch, Contribution Guide, etc. 
/kernels/ 
/rtl/ 
    /include/ -> Headers. 
    /modules/ -> RTL Design.  
/tb/ 
    /formal/ -> Formal assertions/bind files. 
    /unit/ -> .sv Testbenches 
    /uvm/ -> UVM Testbenches
/waves/ -> `.do` Waveform Scripts (QuestaSim). 
/scripts/ 
/aihw-ppci-compiler/ -> PPCI Infra, adapted for Atalla SW Stack.
/AMP-Sim/ -> Cycle-Accurate Simulator of Atalla x01. 
/UVM_1.2/ -> UVM Core Libs. 
/LICENSE 
/Makefile  

Note: Synthesis flows are NDA-protected, and SoCET students are required to reach out to their GTAs to get setup with Design-Flow's PD flows.

• We enforce high standards for our "Design Logs", logs where contributing members explain their design choices and micro-architectural details to ensure their work is reproducible. You can find them here.