Core for QuantiumV - A RISC-V SoC collab work.

RISCV SoC Collab work.

Comprehensive roadmap for aspiring Embedded Systems Engineers, featuring a curated list of learning resources

hilite.me converts your code snippets into pretty-printed HTML format, easily embeddable into blog posts, emails and websites.

Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

A repository contains all sort of cheat-sheets for various things.

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

A very simple example of how to use Verilator

ECP5 based FPGA Board

A simple three-stage RISC-V CPU

RISC-V Instruction Set Manual

8 bit computer using sap logic

Marginally better than redstone

A very simple RISC-V ISA emulator.

lowRISC Style Guides

A High-performance Timing Analysis Tool for VLSI Systems