Thanks to visit codestin.com
Credit goes to github.com

Skip to content
View SRB-TYAGI's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report SRB-TYAGI

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
SRB-TYAGI/README.md

Hi πŸ‘‹, I'm SOURABH TYAGI

A passionate VLSI Enthusiast from India

πŸš€ About Me

I am a B.Tech Electronics and Communication Engineering student at VIT-AP, specializing in VLSI design with hands-on experience in RTL-to-GDSII flow, analog/digital/mixed-signal circuits, and semiconductor technology. My academic journey is complemented by internships and projects that bridge theory with real-world applications in chip design, FPGA systems, and circuit verification.

πŸ’» Core Expertise

  • VLSI Design: Verilog, SystemVerilog, UVM, RTL-to-GDSII, Static Timing Analysis
  • EDA Tools: Cadence Virtuoso, Genus, Innovus, Tempus, Voltus, Xilinx Vivado
  • Circuit Design: 6T SRAM, Op-Amps, Amplifiers, Data Converters, Logic Circuits
  • Programming: Python, Java, C, Embedded C | MATLAB, ROS
  • Hardware: Oscilloscope, Multimeter, Signal Generators, FPGA (Zynq-7000)

πŸ“Œ Key Experiences

  • IIT Jammu (Summer Intern, 2025): Designed Verilog-based hardware blocks for a Quantum Key Distribution (QKD) pipeline on FPGA, achieving sub-Β΅s latency and <10% LUT usage. Integrated radix-16 NTT architecture for secure key compression.
  • MANIT Bhopal (Summer Intern, 2024): Developed a 3-DOF robotic manipulator with trajectory planning in MATLAB, integrating voice and vision-based control in ROS.

πŸ“š What I’m Learning

  • Physical Design and Static Timing Analysis.
  • Enhancing skills in AWS Cloud Computing with a focus on IaaS, PaaS, SaaS.

πŸ› οΈ Tech Stack

  • Languages: C, Java, Python, Verilog
  • VLSI Tools: Cadence Virtuoso, Xilinx Vivado,Eda plyground.
  • Cloud Platforms: AWS

πŸ‘― I’m looking to collaborate on

  • VLSI Design Projects: Digital/analog circuit design, ASIC/FPGA development, combinational/sequential circuits.
  • FPGA and Hardware Design: Working with Zynq-7000, Verilog, or VHDL projects.
  • Cloud Computing for VLSI: Integration of cloud platforms like AWS for VLSI simulation and design workflows.
  • Open Source Projects: Anything related to Electronics, Semiconductors, or Digital Design.

🀝 I’m looking for help with

  • Advanced Physical Design: Gaining deeper insights into Physical Design flows, Timing Closure, and Layout Optimization.

  • RTL to GDSII Flow: Understanding best practices for synthesis, placement, routing, and verification.

  • Static Timing Analysis (STA): Looking for guidance on mastering clock tree synthesis (CTS) and timing analysis techniques.

  • Power Optimization Techniques: Learning more about low-power design methodologies for digital circuits.

☁️ AWS Cloud Computing Skills

🌐 Key Skills

  • Cloud Services: Proficient in IaaS, PaaS, SaaS models
  • AWS Services: Familiar with EC2, S3, RDS, Lambda, and IAM
  • Cloud Architecture: Knowledge of designing scalable and reliable cloud architectures

πŸ“š Currently Learning

  • Exploring AWS services like AWS Lambda for serverless computing and AWS CloudFormation for infrastructure as code.

srb-tyagi

srb-tyagi

πŸ“« How to reach me

Connect with me:

https://www.linkedin.com/in/srb-tyagi

Languages and Tools:

aws c html5 java linux matlab python

srb-tyagi

Β srb-tyagi

srb-tyagi

Pinned Loading

  1. Cadence-Virtuoso_Projects Cadence-Virtuoso_Projects Public

    1

  2. QKD-project QKD-project Public

    Quantum Key Distribution (QKD) Post-Processing: C++ simulation of sifting & error correction, and Verilog HDL implementation of hardware-optimized sifting and privacy amplification using NTT-based …

    C

  3. RISC-V-PROCESSOR RISC-V-PROCESSOR Public

    This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standar…

    Verilog 3 2

  4. 50_Days_Cadence_Virtuoso_Projects 50_Days_Cadence_Virtuoso_Projects Public

    1

  5. SRAM SRAM Public