Thanks to visit codestin.com
Credit goes to github.com

Skip to content
View Siddharth13s's full-sized avatar

Block or report Siddharth13s

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

Verilog 12 1 Updated Jul 31, 2024

UWB and high gain Microstrip Antenna for detecting the presence of tumor in human skin using S-band and C-band microwave frequency

1 Updated May 25, 2024

complete program for RISC-V RV32I based 5-Stage Pipelined Processor with Hazard Control

Verilog 1 Updated May 29, 2024