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SilviaB24/README.md

Hi there, I'm Silvia! 👋

I am a Dual Degree Master's student (Politecnico di Torino & UIC) specializing in Electronic Design Automation (EDA) and Physical Design. I bridge the gap between Hardware Design (RTL) and Software Engineering (Algorithms), building tools to optimize chip performance.

🔹 Status: STEM OPT Eligible (USA) - Available for Summer 2026 Internships.

🚀 Technical Stack

EDA & Hardware Verilog VHDL Synopsys Cadence Tcl

Software & Algorithms Python C++ Git Linux

🛠 Selected Projects

  • DLX Processor (RTL-to-GDSII)

    • Full ASIC implementation of a 32-bit RISC CPU using 45nm Nangate technology.
    • Tools: VHDL, Synopsys DC, Cadence Innovus.

  • VLSI Fault Simulator

    • Python CLI tool for stuck-at fault simulation with Equivalence & Dominance collapsing.
    • Stack: Python, Algorithms, ISCAS-85.

  • Slack-Aware Leakage Optimizer

    • TCL automation script achieving >90% leakage reduction via dual-Vth swapping.
    • Stack: Tcl, Synopsys PrimeTime/DC.

  • Force-Directed HLS Scheduler

    • C++ implementation of Force-Directed Scheduling for High-Level Synthesis.
    • Stack: C++, Graph Algorithms.

⚡ Fun Fact

When I'm not optimizing timing paths, I draw on the discipline from my background as a Competitive Athlete (Italian Serie A Primavera Soccer & Futsal Regional Champion). I bring the same resilience from the field to the lab.

Pinned Loading

  1. DLX-Processor-Portfolio DLX-Processor-Portfolio Public

    Full RTL-to-GDSII implementation of a 32-bit RISC Processor. Features Physical Design (P&R), CTS, and Timing Closure using Synopsys DC & Cadence Innovus.

  2. VLSI-Fault-Simulator VLSI-Fault-Simulator Public

    Python-based VLSI Fault Simulator for ISCAS-85 benchmarks. Features a CLI engine for Stuck-at Fault injection, Logic Simulation, and reduced fault lists via Equivalence & Dominance collapsing algor…

    Python

  3. Low-Power-Optimization-TCL Low-Power-Optimization-TCL Public

    TCL-based heuristic engine for Post-Synthesis Leakage Power Optimization using Synopsys Design Compiler. Implements a Slack-Aware Batch & Revert algorithm.

    Tcl

  4. Force-Driven-ML-RCS Force-Driven-ML-RCS Public

    C++ HLS Scheduler implementation tackling the Resource-Constrained Scheduling problem with Force-Directed heuristics.

    C++