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GHDL ignores VUNIT_GHDL_PATH environment variable

Status: Open.

#1136 In VUnit/vunit;

· Lucas-KB opened on Oct 15, 2025

modelsim support for vhdl 2019

Status: Open.

#1135 In VUnit/vunit;

· rpatel3001 opened on Oct 10, 2025

[FEATURE REQUEST] Produce a warning when attempting to set NVC <code>--exit-severity</code> via <code>nvc.sim_flags</code>

Status: Open.

#1132 In VUnit/vunit;

· JHertz5 opened on Sep 3, 2025

Different behavior between GHDL/ModelSim and NVC for VHDL file access

Bug

Status: Open.

#1131 In VUnit/vunit;

· jorkrohn opened on Aug 25, 2025

check_axi_stream not detecting errros in 5.0.0.dev6

Enhancement

Status: Open.

#1127 In VUnit/vunit;

· obruendl opened on Jul 30, 2025

[QUESTION] Why do component instantiations create dependencies on entity/module implementations?

Enhancement

Status: Open.

#1126 In VUnit/vunit;

· std-max opened on Jul 11, 2025

[FEATURE REQUEST] Improve timing report when <code>run_all_in_same_sim</code> is used

Status: Open.

#1125 In VUnit/vunit;

· nselvara opened on Jul 9, 2025

question: support to extended identifiers in the VUnit VHDL Parser?

Status: Open.

#1120 In VUnit/vunit;

· rafaelnp opened on Jun 8, 2025

[BUG] Simulation Discrepancy Between VUnit <code>v5.0.0-dev.4</code> and <code>v5.0.0-dev.5</code> with Intel's <code>altclklock</code> IP

Status: Open.

#1119 In VUnit/vunit;

· nselvara opened on May 30, 2025

Parsing of VHDL configurations does not handle spaces

Enhancement

Status: Open.

#1112 In VUnit/vunit;

· jobtijhuis opened on Apr 28, 2025

Add reset port to VC axi_lite_master.vhd

Enhancement

Status: Open.

#1110 In VUnit/vunit;

· rafaelnp opened on Apr 20, 2025

Output the command that sends to the simulator

Enhancement

Status: Open.

#1109 In VUnit/vunit;

· yangyt96 opened on Apr 18, 2025