The VC AXI4 Lite manager lacks the reset port, making it difficult to perform a verification on scenarios where the DUT needs a reset to initialise its internal logic.

In the case of an asynchronous reset, it is possible to work around this problem, by triggering a very short reset before the first clock rising edge:

		test_runner_setup(runner, runner_cfg);

		if run("testcase") then
			rst <= '1';
			wait for 0.1 ns;
			rst <= '0';
                       -- test case starts here
                      -- ...
                      -- ...

Adding the reset port would make this VC more flexible and easier to use on different verification scenarios.