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Showing results
SystemVerilog 50 19 Updated Oct 30, 2021

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

VHDL 470 40 Updated Oct 21, 2025
Java 119 10 Updated Oct 16, 2025

ULPI Link Wrapper (USB Phy Interface)

C++ 32 11 Updated May 3, 2020

STM32-style peripheral modules (GPIO, TIM, UART, etc.) and general graphic modules (drivers, algorithms ...) written in Verilog/Chisel/SpinalHDL with APB/AHB/AXI interfaces. Includes a RISC-V SoC e…

VHDL 5 Updated Oct 20, 2025

Docker implemented in around 100 lines of bash

Shell 12,535 750 Updated Dec 9, 2017

🧪 single header unit testing framework for C and C++

C++ 930 69 Updated Aug 31, 2025
Verilog 12 1 Updated Mar 30, 2025

🌊 Digital timing diagram rendering engine

JavaScript 3,271 391 Updated Jul 10, 2025
C++ 147 2 Updated Aug 30, 2025

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

SystemVerilog 22 Updated Sep 19, 2025

A hardware component library developed with ROHD.

Dart 104 33 Updated Oct 24, 2025

Si5351-Module-Clone with low PPM TCXO! Drop-in replacement for the Adafruit's Si5351 module. 3.3v ONLY!

HTML 26 4 Updated Jul 23, 2025

🟢 super fast 🚀 and tiny 🐥 embedded device 𝘾 printf-like trace ✍ code, works also inside ⚡ interrupts ⚡ and real-time PC 💻 logging (trace ID visualization 👀)

C 828 82 Updated Nov 5, 2025

SpinalHDL components for Corundum Ethernet

Scala 13 2 Updated Aug 16, 2023

Bad Apple in 65kB or bust.

C 35 3 Updated Oct 8, 2025

Zero-dependency single-file C header for VPX coding, a form of Arithmetic coding.

C 20 Updated Aug 17, 2025

The single instruction C compiler

C 10,007 408 Updated May 29, 2024

A comparison of 1st and 2nd order sigma delta DAC for FPGA

VHDL 59 6 Updated Jan 12, 2021

ExtIO_sddc.dll - BreadBoard RF103 / HDSDR

C 95 31 Updated Nov 1, 2025

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

Jupyter Notebook 214 39 Updated Apr 29, 2025

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

Verilog 48 13 Updated Jul 4, 2019

The official NFFT library repository

C 181 49 Updated Nov 1, 2025
Julia 7 1 Updated Apr 7, 2025

The RTL8812AU driver that simply devours its competitors,enable tx mode.master branch for termux and android-compat branch for APP|支持双向传输的安卓用户态8812au网卡驱动,master分支用于termux,android_compat分支用于安卓APP

C 6 1 Updated Dec 9, 2024

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …

SystemVerilog 70 15 Updated Jul 14, 2025

micro read line library for small and embedded devices

C 268 84 Updated Oct 29, 2023

upstream: https://github.com/sophgo/sophpi/tree/sg200x-evb

Shell 52 18 Updated Oct 11, 2025
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