[Earlgrey] Silver Release v1

This first Silver release should be treated as a "pre-release",
since several details still have to be aligned and connected.

For instance:
- some DFT hooks may still be missing,
- SDC constraints require tuning, especially on
  the fast interfaces (USB, dedicated SPI),
- there are several missing infrastructure
  connections (e.g. life cycle),
- the pinout and padring are not entirely finalized,
- a couple of IPs are not yet stable or even not
  present (e.g. SPI host),
- the memory sizes have to be finalized,
- and there are still several lint errors that need to be fixed.

The purpose of this "pre-release" is to get PD started using
the current state on master, instead of having to rely on
the outdated Bronze branch.

[Earlgrey] Bronze Release v11 Revisions

1. Split OTBN DMEM into two physical regfile macros.
   This required a few modifications in ramgen.

2. Add release script, generate and check in golden file list.

3. Add new BIST IP and create dummy connections in flash wrapper.

4. Align OTP wrapper interface between master / bronze.

5. Carry over newer DVSim scripts to bronze.

6. Check in new SDC updated SDC file.

[Earlgrey] Bronze Release v10 Revisions

1. Minor fix to PWR sequencing signal in OTP (remove _h suffix of one signal)

2. Add prim_flop technology cell to foundry repo

3. Instantiate prim_flop in OTP wrapper for DFT tests

[Earlgrey] Bronze Release v9 Revisions

1. Fix for pattgen IRQs and portwidths

2. Multi-driven signal fix for OTP

3. Interface and shimming logic updates for OTP

[Earlgrey] Bronze Release v8 Revisions

1. Several lint cleanups (both in RTL and waiver files)

2. Merge in Nuvoton AST delivery

[Earlgrey] Bronze Release v7 Revisions

1. Add AscentLint flow with ASIC prim wrapper views
and macro Libs.

2. Disallow tri nets to be written into the synthesized
verilog netlist in the DC flow.

[Earlgrey] Bronze Release v6 Revisions

1. Vendor soft-IP is now checked into the foundry repo,
hence no need for anoter `cores-root` pointing to the
library path, with an extra core file that is not
source-controlled.

2. The OTP macro has been instantiated and wired up
with dummy connections

[Earlgrey] Bronze Release v5 Revisions

1. Revise IO delays of USB due to timing violations
2. Set case analysis on critical pad attributes
3. Instantiate the real flash macro

[Earlgrey] Bronze Release v4 Revisions

1. The SPI Device DIO pads where missing and have been added in this revision.
2. Remove tie-off of unused inout ports in order to avoid tran stratements in synthesized netlist.

[Earlgrey] Bronze Release v3

Revisions:
- Remove `prim_pad_wrapper` from `padctrl` and connecting `warl_mask` to
  1

Now, it shows -160ns WNS. Pad macro consumes most of the time.
input/output delay may need some tuning.