The Prince lightweight block cipher in Verilog.

Hardware implementation of the poly1305 message authentication function.

Verilog 2001 implementation of the ChaCha stream cipher.

Hardware implementation of the hash function md5

Low-cost LS/FS/HS USB sniffer with Wireshark interface

sdcc header file STC12C5A60S2.h and REG52.h

一个用于将 Keil C51 语法转换为 SDCC 兼容语法的程序

Unmanaged Switch Application Software for VSC7420/VSC7421/VSC7422

command line tool for frequent amaranth HDL tasks (generate sources, show design)

FPGA mandelbrot accelerator via high speed/super speed USB

Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)

A templated C++ library for big integers and large floating point numbers.

Machine learning on FPGAs using HLS

Blackwire SpinalHDL components implementing WireGuard primitives

ESP32 Driving SSD1306 OLED LCD and Running LVGL Library

100Gbps Intrusion Detection and Prevention System

Framework for FPGA-accelerated Middlebox Development

Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto

A powerful, hackable FPGA-based audio multitool for Eurorack.

Bluespec Compiler (BSC)

Intermediate Language (IL) for Hardware Accelerator Generators

EDA Tools: Altera Quartus 13 Dockerfile

Low Level Hardware Description — A foundation for building hardware design tools.

Connect your devices into a secure WireGuard®-based overlay network with SSO, MFA and granular access controls.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

A C++ implementation of ChaCha20 & Poly1305 stream cipher described in RFC - 8439.

A powerful coding agent toolkit providing semantic retrieval and editing capabilities (MCP server & other integrations)

LiteX based White Rabbit PCIe NIC developped for Warsaw University of Technology.