Self-contained RTL to GDS flow for simple chip designs

3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.

An abstraction library for interfacing EDA tools

FazyRV Hachure is a System on Chip that integrates seven different variants of the bit-serial FazyRV RISC-V core in one chip for testing and research purposes.

3-stage RV32IMACZb* processor with debug

nextpnr portable FPGA place and route tool

A set of utilities that can be used to develop digital IPs in Verilog HDL.

Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP

AHB3-Lite to Wishbone Bridge

Simulator for InfiniTime user interface without needing a PineTime

Firmware for Pinetime smartwatch written in C++ and based on FreeRTOS

A tiny RISC-V instruction decoder and instruction set simulator

TinyQV - Crowdsourced Risc-V SoC

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

State-of-the-Art Source Code Plagiarism & Collusion Detection. Check for plagiarism in a set of programs.

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

A model manager for Civitai