⚙️🗑️ A GitHub Action to free disk space on an Ubuntu runner.

matrix-coprocessor for RISC-V

An energy-efficient RISC-V floating-point compute cluster.

Optimized RISC-V FP emulation for 32-bit processors

arXiv LaTeX Cleaner: Easily clean the LaTeX code of your paper to submit to arXiv

The OpenPiton Platform

Website for the OpenROAD tutorial held at the MICRO 2022 conference

An ATE Pattern Generator for PULP chips and JTAG Taps in general

OpenXuantie - OpenE906 Core

Working draft of the proposed RISC-V V vector extension

Package manager and build abstraction tool for FPGA/ASIC development

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

A dependency management tool for hardware projects.

An Emacs framework for the stubborn martian hacker

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Density test bench for RISCV - "Compress extension"

The main Embench repository

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

lowRISC Style Guides

The OpenSource Disassembler