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lbetlej

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Commits on Mar 11, 2020

• cavs: align look and feel of cavs 1.8/2.x shim headers

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• cavs: clean up of bit setting macros in shim headers

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Commits on Mar 5, 2020

• cavs: clk: add Kconfig option to select default ro clock

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Commits on Jan 31, 2020

• cavs: enable power gating of unused memory banks for cavs 2.x hw

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• cnl: make boot loader code more readable

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• cnl: remove an obsolete constant

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Commits on Dec 20, 2019

• tools: add community key signature to sof_ri_info

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  Marcin Maka

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Commits on Dec 10, 2019

• tools: add APL key signature to sof_ri_info

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Commits on Dec 3, 2019

• detector: fix bug in synthetic load calculation

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Commits on Nov 21, 2019

• Remove doxygen warnings during documentation generation

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Commits on Oct 23, 2019

• cavs: enable power gating for lp/hpsram on d3 entry

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• cavs: deduplicate power down sequence for cavs platforms

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Commits on Oct 15, 2019

• cnl: Access to HPSRAM power gating status register - macro updated

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• lib: Make sure shifted quantity is treated as 64bit type

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Commits on Mar 11, 2019

• comp: selector: add support for binary configuration data

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• test: selector: add support for binary configuration data

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Commits on Mar 10, 2019

• logger: add KPB component name

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• logger: add channel selector component name

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Commits on Mar 4, 2019

• test: kpb component name fixed in a configuration file

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Commits on Feb 1, 2019

• ipc: keyword detection (KD) notification - ipc definition

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Commits on Jan 25, 2019

• pm: clean up of power_down.s files

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Commits on Nov 23, 2018

• Power up only subset of HP SRAM banks on FW init (CannonLake)

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Commits on Nov 21, 2018

• Fixes for macros used for bit masks creation.

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Commits on Nov 19, 2018

• LDO Control - unification of control macros for LDOCTL bits

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Commits on Nov 16, 2018

• LDO control on D0->D3 transtion for CannonLake

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Commits on Nov 13, 2018

• Added SRAM power gating on D3 entry for cAVS 1.8 (i.e. Cannonlake).

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Commits on Oct 24, 2018

• Set SRAM LDO off on power down - additional power gating on D0->D3 path.

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Commits on Jul 24, 2018

• Power gate DSP SRAM banks for D0->D3 flow (#135)

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