feat: hint opcode implementation #108

bfan05 · 2024-07-02T16:49:20Z

resolves https://linear.app/intrinsictech/issue/INT-1696/implement-hint-opcodes

linear · 2024-07-02T16:49:22Z

We need to support the instructions AsmInstruction::Hint and AsmInstruction::HintLen when we convert from AsmInstruction to Instruction.

This involves adding a new opcodes Hint and HintLen. The VirtualMachine should take as input some input encoding, such as Vec<Vec<[F; 4]>>, where each element is the serialization of an input element. (SP1 calls this the witness_stream.) Then the opcodes do the following:

hint a: Pop the front element next_input off of witness_stream and write all the elements of next_input consecutively starting at [a]_d (i.e., set up vm state so that this happens in trace generation).
hint_len a: Peek the front element next_input of witness_stream and write the length of this element to [a]_d.

zlangley

Modify the test_io test to compile and run its program and make sure it passes.

vm/src/cpu/trace.rs

zlangley

Is this generating trace rows to write the hints into the memory trace?

compiler/src/conversion/mod.rs

vm/src/memory/offline_checker/mod.rs

bfan05 · 2024-07-09T16:33:55Z

Is this generating trace rows to write the hints into the memory trace?

@zlangley no, since the accesses are not being pushed to the accesses array, which is the thing used to generate trace rows

vm/src/memory/offline_checker/mod.rs

compiler/src/conversion/mod.rs

compiler/tests/io.rs

vm/src/cpu/mod.rs

jonathanpwang

For safety, I think all HINTs should be at timestamp 0. If the HINT opcode does not even show up in the program code (so it is ignored by the CpuChip), then it is unsound to allow arbitrary HINTs at any timestamp: that would mean there's no way to tell if memory is properly constrained (how would you know the difference between a program where I inserted a bunch of random hints into memory trace in between every read vs. a normal program?). The fact that tests pass with this current implementation means there's definitely something fishy related to INT-1708.

Separately, the AsmInstruction::Hint needs to be able to allow e = 1 or 2 for compiler purposes. @TlatoaniHJ can you confirm and also see if there's a suggested fix?

vm/src/memory/offline_checker/air.rs

vm/src/memory/offline_checker/mod.rs

vm/src/memory/offline_checker/trace.rs

vm/src/cpu/trace.rs

vm/src/memory/offline_checker/mod.rs

zlangley

lgtm

jonathanpwang

LGTM

* feat: hint opcode implementation * wip * wip * wip * wip * wip * feat: hint * chore: add comment for to_field change * chore: use CPU_MAX_ACCESSES_PER_CYCLE * chore: add max_access_per_instruction for HINT * chore: address comments * wip * feat: integration test for hint * chore: address comments * chore: add HINT to Core instruction list * Modify hint instruction to write length + contents together * Remove AsmInstruction::HintLen * add comment for or * format * chore: fix lints * chore: fix test_vm_hint * chore: uncomment felts --------- Co-authored-by: Zach Langley <[email protected]>

* Cuda tracegen + tests for Rv32DivRem * review comments

feat: hint opcode implementation

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bfan05 requested a review from zlangley July 2, 2024 16:49

zlangley requested changes Jul 2, 2024

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bfan05 added 5 commits July 2, 2024 17:53

wip

eb4f2d3

merge main

838c35e

wip

3d48a39

wip

fe42e37

wip

d5b67d8

jonathanpwang marked this pull request as draft July 9, 2024 04:02

bfan05 added 6 commits July 9, 2024 10:41

wip

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feat: hint

7d23b62

chore: add comment for to_field change

fcad7ba

Merge branch 'main' into feat/vm-hint

7f23fac

chore: use CPU_MAX_ACCESSES_PER_CYCLE

1435283

chore: add max_access_per_instruction for HINT

40a385d

bfan05 marked this pull request as ready for review July 9, 2024 15:30

bfan05 requested review from TlatoaniHJ, jonathanpwang and zlangley July 9, 2024 15:31

zlangley reviewed Jul 9, 2024

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bfan05 added 4 commits July 9, 2024 13:11

chore: address comments

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merge main

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wip

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feat: integration test for hint

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jonathanpwang reviewed Jul 10, 2024

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TlatoaniHJ reviewed Jul 10, 2024

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bfan05 and others added 4 commits July 10, 2024 12:52

chore: address comments

fb2c201

chore: add HINT to Core instruction list

2efb9bf

Modify hint instruction to write length + contents together

371954d

Remove AsmInstruction::HintLen

c6fea1a

zlangley requested review from jonathanpwang and zlangley July 10, 2024 20:09

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bfan05 and others added 5 commits July 10, 2024 16:12

add comment for or

b57a0d6

format

5b52c7b

chore: fix lints

eaff4d7

chore: fix test_vm_hint

2b41e27

chore: uncomment felts

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jonathanpwang approved these changes Jul 10, 2024

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bfan05 merged commit 5609fa1 into main Jul 10, 2024

bfan05 deleted the feat/vm-hint branch July 10, 2024 20:50

jonathanpwang pushed a commit that referenced this pull request Aug 14, 2025

feat: cuda tracegen + tests for divrem (#108)

f03aaca

* Cuda tracegen + tests for Rv32DivRem * review comments

jonathanpwang pushed a commit that referenced this pull request Aug 14, 2025

feat: cuda tracegen + tests for divrem (#108)

a4fe8f7

* Cuda tracegen + tests for Rv32DivRem * review comments

jonathanpwang pushed a commit that referenced this pull request Aug 19, 2025

feat: cuda tracegen + tests for divrem (#108)

b216694

* Cuda tracegen + tests for Rv32DivRem * review comments

feat: hint opcode implementation #108

feat: hint opcode implementation #108

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bfan05 commented Jul 9, 2024 •

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