Feat/poseidon2 #95
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Feat/poseidon2 #95
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Refactor CPU tests, add positive tests for CPU, fix relevant bugs in AIR and trace generation
Add program chip, move instruction frequency calculation to CPU trace, add positive tests for program
Include program chip (+ positive tests) in commit (forgot to last time), add negative tests, change cpu::trace::Memory to return 0 for cells that haven't been written to, change CPU's generate_trace to terminate when pc goes out of bounds (previously was only when pc = -1)
Add dependency on derive-new, derive new for Instruction, use that in cpu/tests/mod.rs, add comment explaining program used in test_negative.
Refactor MemoryAccess for eventual merge with memory::MemoryAccess. Analogously change MemoryAccessCols.value to .data for consistency.
Add terminate instruction, and use to make sure CPU trace height is power of 2. Also make sure that program trace height is power of 2 by adding jumps to same instruction. Refactor tests using ::from_size to construct Instruction, MemoryAccess, ArithmeticOperation.
…ark proving engine
… quotient poly degree back to 7, remove debug statements
jonathanpwang
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jonathanpwang
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* Cuda tracegen + tests for Rv32HintStore * fix: MemoryWriteAuxAdapter * fill zero for some fields
jonathanpwang
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* Cuda tracegen + tests for Rv32HintStore * fix: MemoryWriteAuxAdapter * fill zero for some fields
jonathanpwang
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Aug 19, 2025
* Cuda tracegen + tests for Rv32HintStore * fix: MemoryWriteAuxAdapter * fill zero for some fields
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Wide poseidon2 permute on a width 16 state. (Should also support width 24, but untested)
Description of function and implementation on HackMD.
Supports
requestso that other functions can statefully generate output and then retrieve the generated trace.