* Added modularity to the ITI module to ensure compatibility with an
  instruction-by-instruction encoder configuration (`block_mode = 0`)
* Moved the code to corev_apu/instr_tracing/ITI for better project
  structure
* Modified the `iti_test.sh` to accept an executable as an argument
* ITI is integrated into `ariane_xilinx.sv` and `ariane_testharness.sv`

* Add `dpti_ctrl.vhd` from Digilent in the `ariane_xilinx.sv` platform
* Add in the fpga flow the tcl files to build `xlnx_dpti_clk` needed for
  the dpti_ctrl
* Add `slicer_DPTI.sv` to convert encapsulated packet (320 bits) into
  slices (8 bits)
* Add constraints in `ariane.xdc` and `genesy-2.xdc` to correctly
  synthesize with Vivado 2018.2
* Modify the Makefile to add dpti in the fpga build

* Adding script for debug and format conversion in /Decapsuler
* Adding in /SW the Receiver_DPTI that catch slices, reconstruct
  encapsulated packet and decapsulate them
* Adding json files in /SW/FPGA_auto to custom Vscode in order to automate remote
  debugging  (with openocd, gdb)

* Add Documentation about Instruction Tracing, the work done, the choice
  made, the work that remains to be done
* Upgrading the previous CI Test using the referenceFlow from the
  E-Trace Specification for greater robustness and modularity

Co-authored-by: ALLART Come <[email protected]>