ASIC Engineer · PhD Candidate @ UL Lafayette · Hardware Security & Threshold Logic Gates (Somtimes called Multi-Valued Input Logic the former sounds cooler though)
I design and evaluate secure hardware. My current research blends Threshold Logic Gates (TLGs), logic locking, and compute-in-memory with hyperdimensional computing (HDC). On the practical side, I build flows that span Cadence, Yosys/ABC, and OpenROAD/OpenLane.
- 🔬 Research threads: Hardware Security, Sustainable Circuits/Architectures
- 🧪 Toolchains: Cadence Virtuoso / Liberate, ngspice/Spectre, Yosys + ABC, OpenROAD/OpenLane
- ⚙️ Languages: Python, Verilog/SystemVerilog, TCL, Bash
- ☕ Personality: precise by default, playful on Fridays
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Detecting Vulnerability in Hardware Description Languages: Opcode Language Processing
A. G. Ayar, A. Sahruri, S. Aygun, M. S. Moghadam, M. H. Najafi, M. Margala
IEEE Embedded Systems Letters, 2023.
DOI: 10.1109/LES.2023.3334728 -
HiCTL: High Fan-in Differential Capacitive-Threshold Logic Gate Implementation
A. Sahruri, M. Margala, U. Cilingiroglu
ISQED, 2024.
DOI: 10.1109/ISQED60706.2024.10528704 -
TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates
A. Sahruri, M. Margala
VLSI-SoC, 2025.
Preprint DOI: 10.48550/arXiv.2508.17809
More on Google Scholar → (link above)
Expand for brief abstracts
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Opcode Language Processing (ESL'23): We analyze HDL opcode sequences to surface vulnerability patterns using lightweight language-processing techniques.
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HiCTL (ISQED'24): A high fan-in capacitive threshold logic gate with an offset-compensated comparator; the purely capacitive feedback cuts comparator offset with compact area.
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TLGLock (VLSI-SoC'25): A threshold-logic-centric locking primitive with a reproducible SAT evaluation harness (runtime, clauses, conflicts).
Cadence · Spectre/ngspice · Yosys/ABC · OpenROAD/OpenLane · Vitis-AI · Python · Verilog · SystemVerilog · TCL
- 🧩 Built end-to-end locking → SAT attack → metrics flow with plots & CSVs
- 🧠 Implemented HDC pipelines for key encoding & security evaluation
- 🛠️ Automated PVT characterization (Liberate) and SPICE testbench generation
- 📈 Reproducible research: Makefiles, scripts, and clean figure generation
When I’m not simulating or synthesizing, I’m usually drinking coffee, or renaming signals more times than I care to admit.
Always open to collaborations and good benchmark suites.