Analog Bandgap Workshop

Testfield: T593

A PFD-CP Type-II Fractional-N Phase Locked Loop (PLL) Clock Multiplier Layout in IHP SG13G2 Process

Repository for system verilog labs from cadence

Created AMD-Am2901 chip clone (4-bit ALU) with Cadence Virtuoso from a transistor level, manually creating datapath and generating control via CAD. Skills employed: Cadence Virtuoso, Logic (VLSI) D…

Gm over Id methodology

Index of the fully open source process design kits (PDKs) maintained by Google.

A cloud based virtual training workshop conducted by VSD-IAT for Physical-Verification-using-SKY130

Physical Verification using Skywater 130nm technology

Open source process design kit for 28nm open process

nextpnr portable FPGA place and route tool

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

9-bit SAR in skywater 130 nm

A versatile generative model capable of designing topologies for wide range of analog circuits.

Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation

A repository for showcasing my knowledge of the Verilog AMS programming language, and continuing to learn the language.

This code example demonstrates the different features of I3C Target module such as Hot-Join (HJ), Private Transaction, In-Band Interrupt (IBI), Reset and Common Code Command (CCC). Other compatible…

I2C implementation on Skywater 130nm

In this repository, i have explained what are Mixed Signal Circuits and how to design and implement it using eSim and Makerchip Softwares

Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license