Even if you have a schematic circuit that is correct and does what you want it to do, there is a risk that the corresponding PCB will not work properly. This is because your schematic circuit is ideal, but the printed circuit boards are not. Real circuits have unwanted resistances, capacitances and inductances that must be minimized to be successful.

The stackup is the vertical layout and thickness of several layers (not just copper layers) which compose the PCB. Depending on the manufacturing capabilities, one or more stackup choices are available to the designer.

The designer must decide the usage of each copper layer depending on the stackup. Ideally, each signal trace should lay above a ground plane and below another ground plane (like a sandwich). This help to contain the electrical and magnetic fields, not to reach other layers carrying signals as well, but the thickness of the dielectric material also plays a role.

Depending on its length, a trace could become and antenna for signals of certain wavelength due to resonance, thus irradiating other traces in the same or other layers.

General tips:

• Do not use the same ground (reference) plane for two different voltages.

• If a signal has to pass from one layer to another through the power and ground planes, the latter two must be separated by no more than 0.2mm.

• If a signal layer lies between a ground and a power plane, you will have EMI issues unless you put a second ground plane closer to the power plane.

  BAD idea (3 layers):

  ----------- Ground
  -- -- -- -- Signal
  ----------- Power
  

  BETTER idea (4 layers):

  ----------- Ground
  -- -- -- -- Signal
  ----------- Power
  ----------- Ground (close to Power)
  

  EVEN better idea (4 layers)

  ----------- Ground
  -- -- -- -- Signal
  ----------- Ground
  ----------- Power (close to Ground)
  

In a 2-layer stackup you have almost no impedance control. To reduce impedance, put ground traces (G) between signal traces (S):

G S G S G
- - - - - Signal layer

--------- GND layer

But, the thinner the dielectric core, the better. A flexible PCB is even better.

• A

  ----------- GND
  - - - - - - Signal and power
  
  - - - - - - Signal and power
  ----------- GND
  

• B (for low component density)

  - - - - - - Signal and power
  ----------- GND
  
  ----------- GND
  - - - - - - Signal and power
  

• C (for slightly higher component density)

  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  

• A (best if a power plane is required)

  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  
  ----------- Power
  - - - - - - Signal and GND
  
  ----------- GND
  - - - - - - Signal and power
  

• B

  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  

• C

  - - - - - - Signal and power
  ----------- GND
  
  - - - - - - Signal and power
  ----------- GND
  
  ----------- GND
  - - - - - - Signal and power
  
  ----------- GND
  - - - - - - Signal and power
  

Traces and copper planes play a critical role in heat dissipation. So you must take heat into account. Heat can spread to other layers through vias, which is a good thing. However, note that too much heat dissipation is inconvenient when soldering through-hole components.

Be conscious of hot areas, typically around LDO regulators or components that can receive high currents. If your board works as a power supply to other unknown devices, they could demand high currents and create thermal stress in your board.

Heat dissipates in all directions in the 2D plane. To help with that, you can create tracks leading to big copper areas around the hot spot, acting like a heatsink. Power/GND planes also work as a heatsink. Even if you don’t create copper areas, you should leave enough empty space around the hot spot to dissipate heat.

• As a rule of thumb, you need 15.3 cm² per watt of heat dissipation. If there is air flow, you can cut that number to a half.
• Place a lot of vias behind the hot spot to transfer heat to the power/GND planes.
• If there are multiple hot spots, try to spread them to achieve an even distribution of heat along the whole board.
• Thicker tracks (a manufacturing parameter) will also help.

• Most mistakes come from misinterpretation of data sheets.

• Your model of current flow, learned at the school, does not work in PCBs. In PCBs, displacement current is king and the current return path is the queen. Update your mental model to achieve proper signal integrity:

  • What Every PCB Designer Should Know - Return Current Path (with Eric Bogatin)

• Design for grounding. A good grounding design is critical and is actually more important than digital signals. Two main resources are at your disposal for good grounding: stitching vias and ground planes. For further reading:

  • The Path of Least Impedance: How to Use Return Paths for Better PCB Design
  • How to handle current return path for better signal integrity

• Before going into any design, check your manufacturer’s capabilities and fill the design rules properly in your CAD software. Otherwise, you will lose a lot of time.

• Design the smallest board you can to cut costs down.

• PCBs are much easier to design in 4 layers than in 2 layers, and the extra cost is not so high. The quality of signals is also higher. This makes the design much easier, too.

• Choose carefully your components. Don't settle for the first thing you find in the library.

• Run the following checks often, specially just before sending the PCB to manufacturing:

  • DRC on the schematic.
  • DRC on the PCB design.
  • Make sure your PCB is in sync with the schematic.
  • Rebuild copper areas and planes.

• Copper too close to the board edge could present depanelization.

• If you have several power domains, group components using the same voltage in specific areas.

• If you have EMI or crosstalk issues in your manufactured board, blame yourself. It's a defective PCB design. Don't look for the solution in the schematic.

• As a general design rule, place traces running left-right in one layer and traces running up-down in another layer.

• Spread the tracks as much as you can to avoid crosstalk.

• Put special care to place the following tracks far away from the others:

  • Clock signals. May cause crosstalk.
  • Reset signals. Crosstalk may cause your chips to reset without reason.

• If you have a power/ground plane, you don’t need tracks for them. Use one via per pad, but there are exceptions: if you need the best possible connection between two components, use a track in the same layer (avoid vias).

• Do not place any floating planes or floating copper areas (nor even for heat dissipation). Either connect them to ground or remove them (except for antennas).

• Whenever possible, route power traces on one layer and signal traces on another.

• Avoid corners (90 degree angles) in traces.

• Use copper areas for power, as it provides the best path for current independently of the designed power traces.

Trace impedance is directly proportional to:

• Operating temperature: heat from components and ambient temperature. Inner layers suffer from more heat.
• Trace length. Keep power/ground traces short.

Trace impedance is inversely proportional to copper thickness:

• 1oz/ft² is a standard for most boards.
• 2oz/ft² is recommended for high current applications
• 3oz/ft² is recommended for for power-hungry boards.

So...

• The higher the current, the wider the trace needs to be.
• More copper means more current-carrying capacity.

• Capacitance is directly proportional to the track area (width and length).
• Capacitance is directly proportional to the dielectric constant.
• Capacitance is inversely proportional to the dielectric thickness (distance between copper layers).

There is a capacitance between a track and the ground plane, but also between adjacent tracks.

• Plan power traces first, keep them short and avoid bottlenecks. Route power/ground traces separately from signal traces.

• As a general rule, power/ground traces should be wider than regular tracks. Add a bit of extra width for safety.

• Set a limit on temperature increase (temperature rise) you're willing to allow without compromising reliability. Typically, this is set to 10℃.

• You must design power/ground tracks to cope with the maximum expected current. Use an online calculator for that. For example:

  • Digikey
  • PCBWay
  • Circuit calculator
  • Saturn PCB toolkit

• Power planes are not needed in most digital circuits due to the low currents. Traces are more than enough to handle up to 10 amps.

• A power plane can be harmful when a signal needs to change layers through a via if it interrupts the return current. This creates noise in the return path, exacerbated by the large surface area of the power plane. However, this effect can be counteracted by placing return vias. Another option is to place the power plane just between two ground planes. This way, there is always a return path for signals changing layers.

• If you really need a power plane, choose a layer as close as possible to the ground plane, as this reduces impedance in the return path.

In summary, avoid power planes.

• Use an internal layer as a ground plane (as said before).

• Place one via to the ground plane per ground pad (as said before), as close as possible. Do not create tracks for the ground net.

• Once this is done, and only after this is done, add grounded copper areas to all other layers.

• Always have a ground plane with no interruptions. Do not create obstructions in the ground plane.

• Place the ground plane directly above or directly below the signal layer.

• Use several vias to connect copper areas of ground.

The track width for digital signals is determined by two parameters:

• Stack-up: the thickness and distance between layers, which depends on the particular manufacturer.
• Impedance: as a general rule, target 50 ohm. This value is just a tradeoff.

If available, always use an online calculator from your manufacturer. For example: JLC PCB. If not available, use a generic calculator like the Saturn PCB Toolkit, but take into account that the actual impedance varies due to the manufacturing process. In case of doubt, use a wider trace at first. You can narrow it later.

• The shorter the trace, the better the signal. Place related components close.

• Use straight traces as much as you can.

• Space out parallel traces.

• Place shielding traces or copper areas of ground to separate one trace from another.

• Treat differential pairs as a special case with their own rules.

Two phenomena is the cause of crosstalk: the electric field and the magnetic field. Those fields induce unwanted voltage and current in the victim track, but only when the signal in the aggressor track is changing (high to low or low to high). So, crosstalk is a concern on traces carrying signals in the megahertz range or higher.

• Electric field coupling:

  Can be modeled as a capacitance. The displacement current moves in the two directions. The inducted pulse in the forward direction (compared to the signal in the aggressor track) will get bigger (in voltage) the wider is the coupling area, but short in time. The inducted pulse in the backward direction will stay low in voltage, but wider in time. To avoid this kind of crosstalk (near-end crosstalk or "NEXT"):

  • Place victim traces far away from the aggressor trace. As a rule of thumb, space the traces 5 times their width or more.

  • Place the reference (ground) plane as close as possible to the signal plane. Layer spacing is a manufacturer parameter you can not change, but you can place the reference plane in the most optimal layer. Again, choose your stackup carefully. Avoid two layer PCBs.

  • If you can not space out the traces, minimize the area where the aggressor and the victim runs in parallel close together.

• Magnetic field coupling:

  Can be modeled as an inductance. The displacement current moves in the two directions but in a different way. A positive voltage pulse travels backwards (compared to the signal in the aggressor track) and a negative voltage pulse travels forwards. The inducted negative pulse will get bigger (in absolute voltage) the wider is the coupling area. The inducted positive pulse stay low in voltage, but wider in time. To avoid this kind of crosstalk (far-end crosstalk or "FEXT"):

  • Place the reference (ground) plane closer to the signal plane.

  • If you can not space out the traces, minimize the area where the aggressor and the victim runs in parallel close together.

Note that both inducted pulses in the forward direction cancel out only if the dielectric material above and below the traces are nearly the same. That is not the case in traces running in the top and bottom layers (as air is the dielectric material in one side).

This is not all about crosstalk: both the aggressor and victim (inducted) signals can rebound at both ends of the track and reflect back and forth. To prevent this, a bit of impedance is needed in the line (as the rise and fall times are smoother due to the tau constant). That is the reason to care about controlled impedance in all traces. You want:

• the highest impedance to reduce crosstalk, but
• the lowest impedance to avoid signal distortion (see below).

For further explanation see Crosstalk explained by Robert Feranec and Eric Bogatin.

• For differential pairs to work, you must achieve almost equal length in both traces, but there is room for some length mismatch (credits to Rick Hartley):

  Signal frequency	Rise/fall time	Maximum length mismatch
  100 Mhz	720 ps	50 mm
  250 Mhz	300 ps	20 mm
  600 Mhz	120 ps	9 mm
  1.2 Ghz	60 ps	4.5 mm
  1.56 Ghz	50 ps	3.8 mm
  3 Ghz	25 ps	1.8 mm
  5 Ghz	17 ps	1.2 mm

  As you can see, it's not as critical as people think.

• In a PCB, a differential pair is two transmission lines (not one), each one having an electric field to the ground plane, as any other digital signal. 95% of the energy is between the trace and the ground plane, so don't forget about the reference plane.

• As a result, the distance between traces is not so relevant as people think. It has been proven that each trace can be routed on opposite edges of the PCB and it works. The reason for routing traces together is achieving equal length.

• The differential pair impedance is two times the odd mode impedance. The odd mode impedance is the characteristic impedance minus the coupling impedance. The characteristic impedance is inversely proportional to the distance between signal and ground layers. The coupling impedance is inversely proportional to the distance between both traces. As a result:

  • Tight coupling allows narrower trace widths (easier design), but it may be impossible to manufacture (due to manufacturing constraints) or have higher costs.
  • Loose coupling achieve better signal integrity and meets manufacturing constrains, but requires wider traces that can ruin your design.

• Tight coupling doesn't lower crosstalk. It's a myth.

• Don't route other signals close to the differential pair to avoid crosstalk.

• For USB 2.x and 3.x, target a single-ended 45 ohms impedance and a differential 90 ohms impedance (+/- 15%).
• Most USB-capable chips require a terminating resistor on each trace, typically 20 to 40 ohms. Check the data sheet.
• USB 2.0 works at 240 Mhz.
• USB 3.0 works at 2.5 Ghz.

See USB 2.0 Board Design and Layout Guidelines and USB3.0 Board Layout Guideline.

There is an effective limit on trace length (for digital signals) due to trace capacitance. Capacitance has a direct impact in the rise and fall times of digital signals and can distort squared-shaped waves to sine-shaped waves.

Check the requirements for your digital signal. Trace length is a concern when the signal rise/fall times are short compared to the propagation time. Note that signal frequency is not involved here. Outer layers are 15% faster (more or less) on signal propagation. The following table shows maximum trace lengths for typical signals (credits to Rick Hartley).

Rise/fall times in nanoseconds. Maximum lengths in millimeters.

Further reading:

• PCB Trace Length: Why It Matters and How Long Is Too Long
• Does I2C require length matching?

• Choose the right via:

  • Through-hole vias goes all the way down from the top layer to the bottom layers.
  • Blind vias connect an outer layer to one or more inner layers.
  • Buried vias connect inner layers.

• Larger vias are cheaper. A good via size is 24mil outer diameter and 12mil inner diameter.

• Take care not to place vias that cannot be manufactured. There is a minimum hole size and a minimum copper ring size.

• There is also a maximum current that can go through a via. Use an online calculator.

  • X part

• When a signal is routed from one layer to another, place another via to ground as close as possible to the first one. The ground via becomes the reference for the other via.

• Two or more pads should not share the same via to power/ground planes. Use separate vias in this case. Remember: one via per pad.

• Minimize the number of vias in the same net as they introduce inductance. As an exception, it is useful to put redundant vias at the very output of the power supply (i.e. a regulator) as they carry more amps and reduce heat.

• If you have a power/ground plane, you don’t need to place vias for GND and/or VCC through-hole pads, as they are like oversized vias.

• Vias under pads require a specific manufacturing process and are quite expensive. Avoid them to cut costs down.

• Target minimizing trace length, noise coupling and thermal dissipation, but pay attention to mounting needs.

• There are manufacturing constraints on component spacing. Look for that information before going into further design. Check the component spacing before sending the board to manufacturing.

• This is where component packaging becomes important. It has an impact on mounting costs. Further reading:

  • Ultimate guide to IC package types

• Decoupling capacitors must be close to power pads.

• Polarized parts should be oriented in a standard way.

• Allow access to test points.

• Group related components.

• Place high-speed chips close to connectors.

• Place all the text in just one direction vertical and one direction horizontal.

• Use the largest font size that fits.

• Place useful information about how to use jumpers, headers, etc.

• Always include version or revision information.