A simple ARMv4T interpreter written in C.

The core requires the consumer to provide an MMU implementation via armv4t/mmu.h, which defines the required 8/16/32-bit load/store operations.

• ARM instruction set
• Thumb instruction set
• Big-endian mode

• MMU interface
  • Load/store interface
  • Prefetch/data aborts
• Undefined instruction handling
• Execution aborts
• Interrupts (IRQ/FIQ/SWI)

• Control register (MMU enable, caches, endianness, alignment faults)
• Translation table base
• Domain access control
• Fault status/address (c5, c6)
• Cache/TLB ops
• Identification registers