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A Perl Tk application that runs regression test suites of large digital circuit designs (written in Verilog, VHDL or SystemVerilog) on Cadence Incisive tools, keeps track of coverage data, driven by a (XML) verification plan.
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anassar/CDV
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A Perl Tk application that runs regression test suites of large digital circuit designs (written in Verilog, VHDL or SystemVerilog) on Cadence Incisive tools, keeps track of coverage data, driven by a (XML) verification plan.
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