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@twizmwazin
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I would like to sunset angr-targets, removing this code from angr and archiving the angr-targets repo, removing it from CI. The code has not been developed in many years, and is largely untested. Further, the way it works isn't really aligned anymore with how angr is used to do analysis on embedded systems binaries, such that it likely doesn't have a future. This decision could always be reversed some day if this becomes an active research topic again.

This is motivated by my interest in refactoring the engine interface to improve type correctness and remove kwargs; and removing unmaintained engines should make that process less difficult.

@twizmwazin twizmwazin merged commit 7059a9e into master Jan 6, 2025
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@twizmwazin twizmwazin deleted the refactor/sunset-angr-targets branch January 6, 2025 23:20
@TheMatt2
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TheMatt2 commented Sep 1, 2025

I came across angr-targets, in looking for ways to have angr analyze binaries that have large pre-main procedures, and it is possible 1000x faster to have that code executed in GDB, instead of in angr.

The best workaround I have found so far is to load a coredump, but it seems some properties such as memory regions and the program stack are not successfully recovered by the coredump.

With angr-targets being sunset, are coredumps the intended way to mix concrete and symbolic execution, or is there something else?

@twizmwazin
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That is one option. Another option could be to try out the unicorn or icicle engines in angr, which can do concrete execution much faster than angr can execute vex by itself. A third option, depending on the nature of the pre-main procedure, is to model some of the code as a SimProcedure, executing that in place of emulating the pre-main procedure. If you could post a sample script and binary demonstrating what you are trying to do, I would be happy to try to help see what optimizations could be done.

@konchunas
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Please, if you remove a feature from the code, remove it from documentation as well. I have spent a whole day trying to setup cross-architecture GDB runner only to discover the functionality was sunset. There is still symbion.rst in docs folder and SYMBION_* options in sim_options.py`

@twizmwazin
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Noted, I am removing those now: #5649

@nbars
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nbars commented Sep 11, 2025

Could you please also add a note to the angr-targets repo that it's not supported by upstream angr anymore. I just tried to get it working until I realized that the feature was removed. You may merge this if you like: https://github.com/nbars/angr-targets

Also, adding a note here https://angr.io/blog/angr_symbion/ would probably save some people a lot of time.

Thanks :)

@ltfish
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ltfish commented Sep 11, 2025

It looks like Symbion or something like Symbion are still being used by users and attracting interest from the community. Can someone please elaborate on the exact use cases? This will help us decide if we want to implement a new feature that complements the missing piece(s).

@nbars
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nbars commented Sep 11, 2025

Same as @konchunas, I wanted to use angr for a heavy target (V8) to perform some localized symbolic execution, which the gdb approach seemed to be quite suitable for. Using unicorn unfortunately fails with some IR decoding error. Also, snapshotting the whole state is not suitable since the target allocates quite a lot of memory.

Can I build a memory proxy as a plugin that resolves memory access dynamically, such that I can return concrete values (retrieved from the target) the first time they occur? So basically the way symbion did but far less features and without changes to the angr code base.

@twizmwazin
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Yes it should be possible to write a memory mixin that can retrieve values from a device as you describe. Another potential option is that I have recently implemented an Icicle emulator based engine in angr intended for fast concrete execution. I would be interested to know if it could potentially be useful here. It should be faster than unicorn and any errors during execution I would be happy to take a look at to see if they can be corrected.

@nbars
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nbars commented Sep 15, 2025

Just tested it using the snippet below:

p = angr.Project(TARGET, use_sim_procedures=True)
engine = IcicleEngine(p)

state = p.factory.full_init_state(
    args=[TARGET] + TARGET_FLAGS + ARGS,
    env=ENV,
    remove_options={*angr.options.symbolic},
    add_options={angr.options.ZERO_FILL_UNCONSTRAINED_MEMORY, angr.options.ZERO_FILL_UNCONSTRAINED_REGISTERS},
)

engine.process(state)

I am getting complaints about missing registers, which is kind of odd, at least for cs, ds, etc.

DEBUG    | 2025-09-15 08:53:42,483 | angr.engines.icicle | Register ymm12 not found in icicle
DEBUG    | 2025-09-15 08:53:42,483 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x280, 32, Iend_LE) = <BV256 0x0>
DEBUG    | 2025-09-15 08:53:42,483 | angr.engines.icicle | Register ymm13 not found in icicle
DEBUG    | 2025-09-15 08:53:42,483 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x2a0, 32, Iend_LE) = <BV256 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register ymm14 not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x2c0, 32, Iend_LE) = <BV256 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register ymm15 not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x380, 4, Iend_LE) = <BV32 0x7>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register ftop not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x388, 64, Iend_LE) = <BV512 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register fpreg not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3c8, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register fptag not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3d0, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register fpround not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3d8, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register fc3210 not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3e0, 4, Iend_LE) = <BV32 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register emnote not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3e8, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register cmstart not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3f0, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register cmlen not found in icicle
DEBUG    | 2025-09-15 08:53:42,484 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x3f8, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,484 | angr.engines.icicle | Register nraddr not found in icicle
DEBUG    | 2025-09-15 08:53:42,485 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x408, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,485 | angr.engines.icicle | Register gs_const not found in icicle
DEBUG    | 2025-09-15 08:53:42,485 | angr.storage.memory_mixins.paged_memory.paged_memory_mixin | reg.load(0x410, 8, Iend_LE) = <BV64 0x0>
DEBUG    | 2025-09-15 08:53:42,485 | angr.engines.icicle | Register ip_at_syscall not found in icicle
DEBUG    | 2025-09-15 08:53:42,485 | angr.engines.icicle | Register cs not found in icicle
DEBUG    | 2025-09-15 08:53:42,485 | angr.engines.icicle | Register ds not found in icicle
DEBUG    | 2025-09-15 08:53:42,485 | angr.engines.icicle | Register es not found in icicle

Even though it seems to terminate, I can not get the output of the target. Do I need some other flags?:

DEBUG    | 2025-09-15 08:54:51,578 | asyncio        | Using selector: EpollSelector
In [9]: fs.posix.dumps(1)
Out[9]: b''

DEBUG    | 2025-09-15 08:55:06,421 | asyncio        | Using selector: EpollSelector
In [10]: fs.posix.dumps(2)
Out[10]: b''

I guess I should create a separate issue when I get some time to look into whether anything actually happened and, if not, why.

Thanks!

@twizmwazin
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The debug warnings are as expected, vex tends to have a lot of "extra" registers it uses for its own purposes, or aliases to another register. The segment registers (cs, ds, es) are unused in x86-64, and are not implemented in the sleigh specs which is why you see those errors. Regarding the output, I am unsure. We have a test in CI that ensures posix stdout works on our test binary. A separate issue with instructions to reproduce the issue would be great.

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6 participants