Pinned Loading

1. ariane-axi-memory-verification ariane-axi-memory-verification Public

   SystemVerilog testbench demonstrating AXI4 protocol expertise: fork-join channel independence, randomized stimulus generation, timeout protection, and front-door verification methodology for RISC-V…

   SystemVerilog

2. riscv-branch-tests riscv-branch-tests Public

   Comprehensive assembly test suite for RISC-V branch instructions (BEQ, BNE, BLT, BGE, BLTU, BGEU). Features systematic test cases covering edge cases, boundary values, and various operand combinati…

   SystemVerilog

3. Simple-RISC-V-Design Simple-RISC-V-Design Public

   This repository contains the backup files of a Simple RISC-V Design carried out during industrial training at Dynamic Solution Innovators by a group of 10 people.

   SystemVerilog

4. ASIC-Project-Carry-Look-Ahead-Adder ASIC-Project-Carry-Look-Ahead-Adder Public

   This repository contains a 16-bit Carry-Lookahead Adder implementation designed to reduce propagation delay in binary addition operations. It includes complete RTL design, verification testbenches,…

   MATLAB

5. FaultyLEDDetectionProject FaultyLEDDetectionProject Public

   This repository contains the codes of a faulty led detection system using image processing techniques in MATLAB.

   HTML

6. Optoelectronics_Simulation Optoelectronics_Simulation Public

   This repository contains the essential code for the lab experiments done in the Optoelectronics Lab of BUET, Dhaka, Bangladesh.

   MATLAB