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@vk2seb vk2seb commented Oct 27, 2025

Fix some issues found while flashing v1.0.0 to first 50 Tiliquas:

  • Some external PLLs apparently take a bit longer to lock, which causes longer visual glitches while switching bitstreams. Specifically in the user bitstream -> bootloader direction. This doesn't look so nice, this PR attempts to fix this by:
    • Always disabling the external PLL outputs early in the bootloader sequence (when we return from a user bitstream).
    • Always holding both DVI PLL blocks in reset when the framebuffer is not active.
  • Also, it seems more difficult to reach timing consistently. So I made some changes to the CPU configuration and the blitter pipeline so it's much easier to reach 60MHz consistently. We still don't get there all the time, but it should require less nextpnr runs.

@vk2seb vk2seb merged commit 341414a into main Oct 27, 2025
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