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Design, Implementation, and Testing for single core, single thread RISC-V CPU

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
BasicRISCCPUTestbench.vhd		BasicRISCCPUTestbench.vhd
RxUnit.vhd		RxUnit.vhd
TxUnit.vhd		TxUnit.vhd
alu.bsf		alu.bsf
alu.vhd		alu.vhd
clkUnit.vhd		clkUnit.vhd
clock_reset_start.vhd		clock_reset_start.vhd
con_logic.bsf		con_logic.bsf
con_logic.vhd		con_logic.vhd
control_signals_logic.bsf		control_signals_logic.bsf
control_signals_logic.vhd		control_signals_logic.vhd
control_signals_logic.vhd.bak		control_signals_logic.vhd.bak
control_unit.bdf		control_unit.bdf
control_unit.bsf		control_unit.bsf
control_unit.vhd		control_unit.vhd
control_unit.vhd.bak		control_unit.vhd.bak
cpu.bdf		cpu.bdf
cpu.qpf		cpu.qpf
cpu.qsf		cpu.qsf
cpu.qws		cpu.qws
cpu.vhd		cpu.vhd
cpu.vhd.bak		cpu.vhd.bak
cpu_nativelink_simulation.rpt		cpu_nativelink_simulation.rpt
datapath.bdf		datapath.bdf
datapath.bsf		datapath.bsf
datapath.vhd		datapath.vhd
datapath.vhd.bak		datapath.vhd.bak
instruction_register.bsf		instruction_register.bsf
instruction_register.vhd		instruction_register.vhd
memory_bus_controller.vhd		memory_bus_controller.vhd
memory_interface.bsf		memory_interface.bsf
memory_interface.vhd		memory_interface.vhd
miniUART.vhd		miniUART.vhd
program_counter.bsf		program_counter.bsf
program_counter.vhd		program_counter.vhd
program_counter.vhd.bak		program_counter.vhd.bak
ram_6116.vhd		ram_6116.vhd
register_file.bsf		register_file.bsf
register_file.vhd		register_file.vhd
rom_27C64.vhd		rom_27C64.vhd
sequencer.bsf		sequencer.bsf
sequencer.vhd		sequencer.vhd
sequencer.vhd.bak		sequencer.vhd.bak
shift_control.bsf		shift_control.bsf
shift_control.vhd		shift_control.vhd
uart_lib.vhd		uart_lib.vhd