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aryapandit200408/README.md

Hi there, I'm Arya Pandit! 👋

🎓 Third-year Electronics and Telecommunications Engineering student at Jadavpur University, Kolkata

💻 Tech Enthusiast | Digital Electronics & Digital Signal Processing | Aspiring Technologist

🔧 Technologies & Tools

  • Programming Languages: C, C++, Python, Verilog, System Verilog
  • Hardware & Digital Electronics: Vivado, FPGA, RTL Design
  • Scripting & Automation: Currently learning Tcl

📬 Let's Connect

Feel free to reach out for collaborations, brainstorming, or tech talks!

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  1. JU-Night-Vision-Dataset JU-Night-Vision-Dataset Public

    Developed under the supervision of Dr Sheli Sinha Chowdhury and Mr Asfaq Ali, by Shirshendu Mandal, Srinjan Bhattacharjee, Sauptik Maiti and Arya Pandit.

  2. Beginner_Verilog_Projects Beginner_Verilog_Projects Public

    This is a repository of my personal FPGA projects

    Verilog

  3. Simple_System_Design_in_Verilog Simple_System_Design_in_Verilog Public

    Verilog

  4. Sentiment-Analysis Sentiment-Analysis Public

    In this world of increasing mental problems among the masses, we aim to make a program that can track and notify the parents and authorities of those particularly at risk.

    Jupyter Notebook