Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.

A very simple and easy to understand RISC-V core.

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

RVX10-P: A Five-Stage Pipelined RISC-V Core supporting RV32I + 10 Custom ALU Instructions, developed under the course Digital Logic and Computer Architecture taught by Dr. Satyajit Das, IIT Guwahati.

A machine learning accelerator core designed for energy-efficient AI at the edge.

Clean, portable, tested implementations of post-quantum cryptography

An Implementation of the Number Theoretic Transform

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

Detailed handwritten Notes, in the speech to text format of, Professor Massimo Rudan's course on SEMICONDUCTOR DEVICES, SOLID STATE SENSORS and QUANTUM COMPUTING at the University of Bologna.

C-Implementations of FFT Algorithms.

Simple implementations of the Fast Fourier Transform in various languages

This fork implements a SIMD ISA extension for the OTBN

DUTH RISC-V Microprocessor

High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.

Writing an OS in 1,000 lines.

Writing a sqlite clone from scratch in C

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

A pure python implementation of ML-DSA (FIPS 204) and CRYSTALS-Dilithium

This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU. The project focuses on multiple implementations of the acc…

fuzzing + concolic = fuzzolic :)

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

Numpy-like matrix arithmetic library based on OpenFHE

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1