Good that you notice.
The solution also seems obvious.

@eimiz , @SuperUserNameMan
I looked it up in the databook, and found that it does not need to be aligned when programming E2PROM.

But when programming as FLASH:

But address must be aligned at 32 bit mode read:

After some more experiments I see that address is auto aligned when SWM or 32bit mode is used.
I mean, reading/writing to addresses 13, 14 or 15 will actually read/write to 12.
The databook also seems to indicate that the last two bits of address are not used:

In my tests SWM write works fine with any address.
However SWM read will store wrong value in E2PD0 on last read (after SWM is off) if address is not aligned. That is, PD0 contains PD1 PD2 or PD3 depending on misalignment.
If SWM_off is moved outside loop, then PD0 is correct, but then a dummy read or P2CTL reset is needed before return.

Yep you're right guys. The older 1.0.4.en datasheet also mention the 4 bytes alignement and the fact that EEAR[0:1] are ignored in 32 bits mode.

I can't find the datasheet I was using when i rewrote the EEPROM lib, but I now remember it was the most recent chinese version i found on weibo and that i personally translated it using google translate. I must have messed in this process.

Sorry for the confusion and the bugs guys.

So should we merge and release?

So should we merge and release?

Yes. It looks good and tested by @eimiz .