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written in SystemVerilog
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Verilator open-source SystemVerilog simulator and lint system
A Verilog synthesis flow for Minecraft redstone circuits
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
4 stage, in-order, secure RISC-V core based on the CV32E40P
The multi-core cluster of a PULP system.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
USB 2.0 FS Device controller IP core written in SystemVerilog
USB Full-Speed/Hi-Speed Device Controller core for FPGA