Stars
A machine learning toolkit for log parsing [ICSE'19, DSN'16]
esphome-econet is a package for controlling a Rheem water heater or HVAC system with an esp32 or esp8266 micro-computer.
Alternative firmware for ESP8266 and ESP32 based devices with easy configuration using webUI, OTA updates, automation using timers or rules, expandability and entirely local control over MQTT, HTTP…
Demonstrating systemverilog, verilator and google test for verification
Python GUIs for Humans! PySimpleGUI is the top-rated Python application development environment. Launched in 2018 and actively developed, maintained, and supported in 2024. Transforms tkinter, Qt, …
Simple benchmark for memory throughput and latency
This repo contains driver samples prepared for use with Microsoft Visual Studio and the Windows Driver Kit (WDK). It contains both Universal Windows Driver and desktop-only driver samples.
Random Memory Benchmark for memory power modelling (originally developed by http://www.roylongbottom.org.uk/)
A collection of tips, tricks and links to help you speed up your pytest suite.
The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++
StreamFX is a plugin for OBS® Studio which adds many new effects, filters, sources, transitions and encoders! Be it 3D Transform, Blur, complex Masking, or even custom shaders, you'll find it all h…
Python bindings for slang, a library for compiling SystemVerilog
Dark+ theme for colorblind developers.
An incremental parsing system for programming tools
An abstraction library for interfacing EDA tools
Responsive Flask/SQLAlchemy personal finance app, specifically for biweekly budgeting.
A bash script to search and install extensions from extensions.gnome.org
The CAIA artificial intelligence system of late Jacques Pitrat
Constraint Solving Problem resolver for Python
RDPWrap.ini for RDP Wrapper Library by Stas'M
sebaxakerhtc / rdpwrap
Forked from stascorp/rdpwrapRDP Wrapper Library
alainmarcel / Surelog
Forked from chipsalliance/SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Reposition windows at the click of the mouse