Next-Generation of Chiaki (the open-source remote play client for PlayStation)

❄️ Visual editor for open FPGA boards

Fully Open Source FASOC generators built on top of open-source EDA tools

Bitstream Fault Analysis Tool

Wavious DDR (WDDR) Physical interface (PHY) Software

Wavious DDR (WDDR) Physical interface (PHY) Hardware

Build your hardware, easily!

Fabric generator and CAD tools.

Tools for FPGA Assurance Flows

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

XLS: Accelerated HW Synthesis

FastF1 is a python package for accessing and analyzing Formula 1 results, schedules, timing data and telemetry

Xml Multi-Language Protocol Generator -- code generator for Open DIS

A fully asynchronous, futures-based Kafka client library for Rust based on librdkafka

Silm your kernel with better configuration.

🔐 Encrypts all the Serialize.

CodeHawk C Analyzer: sound static analysis of memory safety (undefined behavior)

A Proof-oriented Programming Language

Automated generation of provably secure, zero-copy parsers from format specifications

Simple verification of Rust programs via functional purification in Lean 2(!)

Remote Procedure Calls for Kerbal Space Program

Model-rocketry aerodynamics and trajectory simulation software

Building seL4 and generating Rust bindings based on feL4 configuration

A Cargo subcommand for working with feL4 projects.