A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

A small, light weight, RISC CPU soft core

A flexible, type-safe SQLx query builder for dynamic web APIs, offering seamless pagination, searching, filtering, and sorting.

List of SpinalHDL projects, libraries, and learning resources.

An abstraction library for interfacing EDA tools

Berkeley's Spatial Array Generator

Hierarchical Asynchronous Circuit Kompiler Toolkit

Multiple dispatch over abstract array types in JAX.

If it quacks like a tensor...

a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

MR1 formally verified RISC-V CPU

A reimplementation of a tiny stack CPU

A Full Hardware Real-Time Ray-Tracer

SpinalHDL - Cryptography libraries

AdderNet ResNet20 for cifar10 written in SpinalHDL

CNN accelerator implemented with Spinal HDL

FPGA friendly Multiport memories (N-read-M-write) based on LVT

Various tools/utilities for PyTorch

[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning

SpinalHDL Hardware Math Library

Scala based HDL

Implementation of the "Online learning of long-range dependencies" paper, NeurIPS 2023

[CVPRW '23] Real-time depth estimation with an event camera and a laser projector

Chisel Fixed-Point Arithmetic Library

ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Rust crate for physics simulation based on the Bullet SDK and modeled after PyBullet (Github Mirror).