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Update CHANGELOG.md for 0.12 release Run Python tests #28: Commit 5ad9ed6 pushed by fdxmw
1m 14s development
development
1m 14s
Update CHANGELOG.md for 0.12 release Build and publish release #28: Commit 5ad9ed6 pushed by fdxmw
16s development
development
16s
Clean up output_to_verilog's newline logic. This simplifies the cod… Run Python tests #27: Commit a3bc638 pushed by fdxmw
1m 17s verilog
verilog
1m 17s
Clean up output_to_verilog's newline logic. This simplifies the cod… Build and publish release #27: Commit a3bc638 pushed by fdxmw
16s verilog
verilog
16s
Minor Verilog output improvements: Move lines with only "begin" to th… Build and publish release #26: Commit bd716e8 pushed by fdxmw
12s verilog
verilog
12s
Minor Verilog output improvements: Move lines with only "begin" to th… Run Python tests #26: Commit bd716e8 pushed by fdxmw
1m 9s verilog
verilog
1m 9s
Improve Verilog output by using sanitized MemBlock and RomBlock names… Run Python tests #25: Commit c4265e9 pushed by fdxmw
1m 14s verilog
verilog
1m 14s
Improve Verilog output by using sanitized MemBlock and RomBlock names… Build and publish release #25: Commit c4265e9 pushed by fdxmw
17s verilog
verilog
17s
Update _NameSanitizer to try appending the current internal_index bef… Build and publish release #24: Commit 07ec4c3 pushed by fdxmw
14s verilog
verilog
14s
Update _NameSanitizer to try appending the current internal_index bef… Run Python tests #24: Commit 07ec4c3 pushed by fdxmw
1m 16s verilog
verilog
1m 16s
Improve Verilog identifier naming, fix two bugs, add tests, refactor … Run Python tests #23: Commit 7be57c8 pushed by fdxmw
1m 21s verilog
verilog
1m 21s
Improve Verilog identifier naming, fix two bugs, add tests, refactor … Build and publish release #23: Commit 7be57c8 pushed by fdxmw
14s verilog
verilog
14s
Fix two bugs, add tests, refactor duplicated code: Build and publish release #22: Commit 5508deb pushed by fdxmw
20s verilog
verilog
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Fix two bugs, add tests, refactor duplicated code: Run Python tests #22: Commit 5508deb pushed by fdxmw
1m 16s verilog
verilog
1m 16s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #21: Commit c94b341 pushed by fdxmw
1m 19s verilog
verilog
1m 19s
Update output_to_verilog to inline temporary wires, using GateGraph: Build and publish release #21: Commit c94b341 pushed by fdxmw
17s verilog
verilog
17s
Update output_to_verilog to inline single-use temporaries, using `G… Run Python tests #20: Commit 0c3041f pushed by fdxmw
1m 17s verilog
verilog
1m 17s
Update output_to_verilog to inline single-use temporaries, using `G… Build and publish release #20: Commit 0c3041f pushed by fdxmw
19s verilog
verilog
19s
Update export_verilog_testbench to use gates. Run Python tests #19: Commit ca47fd9 pushed by fdxmw
1m 20s verilog
verilog
1m 20s
Update export_verilog_testbench to use gates. Build and publish release #19: Commit ca47fd9 pushed by fdxmw
14s verilog
verilog
14s
Initial implementation of GateGraph, an alternative PyRTL logic rep… Build and publish release #18: Commit 3deeedd pushed by fdxmw
12s development
development
12s
Initial implementation of GateGraph, an alternative PyRTL logic rep… Run Python tests #18: Commit 3deeedd pushed by fdxmw
1m 17s development
development
1m 17s
Add more documentation examples and references. Run Python tests #17: Commit 875f56a pushed by fdxmw
1m 10s gate
gate
1m 10s
Add more documentation examples and references. Build and publish release #17: Commit 875f56a pushed by fdxmw
18s gate
gate
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Minor documentation rewording, trying to better explain the differenc… Build and publish release #16: Commit be6a12a pushed by fdxmw
17s gate
gate
17s