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Verilog 1,723 382 Updated Oct 19, 2025

OpenXuantie - OpenC910 Core

Verilog 1,337 355 Updated Jun 28, 2024

Documentation for NVDLA.

HTML 257 120 Updated Jul 25, 2025

An open-source microcontroller system based on RISC-V

C 982 314 Updated Feb 6, 2024
Python 26 3 Updated Apr 24, 2021

The Xyce™ Parallel Electronic Simulator

C 98 11 Updated Oct 27, 2025

An efficient deterministic solver for phonon BTE

Verilog 32 9 Updated Oct 22, 2025

Public files for the ATPlace2.5D, including test cases and certain code.

Python 7 Updated May 16, 2025

Free ChatGPT&DeepSeek API Key,免费ChatGPT&DeepSeek API。免费接入DeepSeek API和GPT4 API,支持 gpt | deepseek | claude | gemini | grok 等排名靠前的常用大模型。

Python 33,860 2,416 Updated Oct 10, 2025

PACT: A Parallel Compact Thermal Simulator

Python 59 12 Updated Sep 12, 2025

MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC (DATE 2025)

Python 10 Updated Jun 3, 2025
Python 34 6 Updated Jun 1, 2021

Source code for Multifidielity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures

Python 19 Updated Oct 17, 2025

Papers on LLM4EDA from 2023 and 2024

44 2 Updated Jul 6, 2024

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)

Python 34 11 Updated May 21, 2025

本项目是一个面向小白开发者的大模型应用开发教程,在线阅读地址:https://datawhalechina.github.io/llm-universe/

Jupyter Notebook 10,555 1,105 Updated Oct 2, 2025

面向开发者的 LLM 入门教程,吴恩达大模型系列课程中文版

Jupyter Notebook 21,953 2,625 Updated Jun 12, 2025

Course to get into Large Language Models (LLMs) with roadmaps and Colab notebooks.

66,237 7,459 Updated Jun 4, 2025

This is my personal static website. It is based on docsify and deployed on GitHUb Pages. You can simply fork it into your repo to have the same website or modify it to fit your thoughts. Click the …

JavaScript 8 1 Updated Oct 28, 2025

KLayout technology files for ASAP7 FinFET educational process

21 4 Updated Feb 5, 2023
Perl 47 12 Updated Apr 8, 2024

SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0

Perl 18 6 Updated Jul 22, 2020

Cell layout generation (MH Multiheight) for DTCO/STCO exploration toolkit.

C++ 12 Updated Oct 6, 2025

ASTRAN - Automatic Synthesis of Transistor Networks

C 65 24 Updated Apr 4, 2022

reference block design for the ASAP7nm library in Cadence Innovus

Verilog 51 15 Updated Jun 25, 2024

Nangate Open Cell Library

Verilog 5 1 Updated Jan 28, 2025
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