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v0.0.0-9308-gc8a4b1383

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This change made single-argument constructors explicit.

Making single-argument constructors explicit avoids unintentional implicit conversions.

PiperOrigin-RevId: 854188570

v0.0.0-9299-g790959d16

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[codegen 1.5] Port & convert module signature generation to a pass

This pass runs on all blocks without signatures in a package and populates them. The latency calculation for pipelined blocks is simplified to use the schedule information, if present.

For signature preservation, we also update block cloning to clone the signature and initiation interval.

PiperOrigin-RevId: 853909739

v0.0.0-9294-g4555839e1

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[codegen 1.5] Improve handling of `invoke` nodes, working towards FFI…

… support

We skip conversion & scheduling for functions with ForeignFunctionData, and add the check for better error reporting if a non-FFI function has not been inlined before block conversion.

Additionally, the Invoke node constructor is updated to use `to_apply->return_type()` for type inference, which should avoid issues with null-pointer dereference in the event that we still end up with an Invoke node referencing a converted function.

PiperOrigin-RevId: 853448289

v0.0.0-9289-g2a8f3b590

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[codegen 1.5] Add reset requirement for valid-output control

If lowering a function with a valid-output control signal, we should always have a reset signal; otherwise we can end up with (pipeline_depth - 1) cycles of garbage at the valid-output signal, potentially signaling "valid" when the output is very much not valid. This required adding reset signal support to our unit tests' RunFunctionalTest logic for this pass.

While we're at it, we also ensure that the source return value is always available in the last pipeline stage by inserting an identity node if necessary - which can be necessary when lowering a no-op function that directly returns one of its inputs. (This mostly only comes up in testing.)

PiperOrigin-RevId: 853045608

v0.0.0-9282-ge3d2852ae

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Enable previously-failing crasher.

Fixes #3269.

PiperOrigin-RevId: 852441042

v0.0.0-9268-gc04bf946d

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Integrate LLVM at llvm/llvm-project@11d9694b757b

Updates LLVM usage to match
[11d9694b757b](llvm/llvm-project@11d9694b757b)

PiperOrigin-RevId: 852027392

v0.0.0-9267-g2ae55dba5

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[codegen 1.5] Make channel lowering respect placeholders

Our node utility function ReplaceWithAnd previously unconditionally dropped all-ones literals - which caused some substantial errors in context of Codegen 1.5's use of literals as placeholders. We instead explicitly block this behavior, while still leaving the utility functions fully flexible for convenience.

While we're at it, we upgrade the utility functions to be able to combine arbitrary literals into a single literal when requested.

PiperOrigin-RevId: 851840930

v0.0.0-9265-g7036f3509

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[codegen 1.5] Fix a pipeline-register insertion bug for I/O & state o…

…perands

After I/O lowering, we previously ended up moving the use of the operands into logic outside of the pipeline stages. Since pipeline register insertion happened after that point, it would think the uses did not need pipeline registers, accidentally linking (e.g.) Sends directly to their inputs with no intervening registers.

To fix this, we temporarily route these uses through identity nodes in the stage where the operation was scheduled, and rely on our dataflow & identity cleanup passes to remove them later.

The same principle applies to state-write operations too.

This lets us re-enable the `BasicDatapathResetAndInputFlop` test.

PiperOrigin-RevId: 851457571

v0.0.0-9256-g91f903e9c

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Integrate LLVM at llvm/llvm-project@14c00c05c13a

Updates LLVM usage to match
[14c00c05c13a](llvm/llvm-project@14c00c05c13a)

PiperOrigin-RevId: 850765800

v0.0.0-9255-gef13f547b

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[codegen 1.5] Implement ChannelToPortIoLoweringPass.

This pass transforms channel operations (Send/Receive) within a `ScheduledBlock` into either block ports or FIFO instantiations.

We also add support for zero-latency, skid, and single-flop buffering on streaming I/O channels. We port helper functions from codegen 1.0 to add registers and the necessary control logic for Ready/Valid/Data interfaces, though we make it simpler by constructing skid buffers as the combination of a zero-latency & register buffer.

Features not yet supported:
- Gating received data (for predicated or non-blocking receives)

PiperOrigin-RevId: 850524913