Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.

NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.

https://caravel-user-project.readthedocs.io

Converts GDSII files to STL files.

A caravan equipped with API for creating bus protocols in Chisel with ease.

Modular hardware build system

⚔️ Debuggable hardware generator

ESESC: A Fast Multicore Simulator

An open-source static random access memory (SRAM) compiler.

M-extension for RISC-V cores.

draws an SVG schematic from a JSON netlist

A graphical user interface for the OpenLANE RTL-GDSII flow

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

Pipelined In-order Core for Artix-7 Arty-35T board

Learning FPGA, yosys, nextpnr, and RISC-V

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

Flexible Intermediate Representation for RTL

Universal utility for programming FPGA

A caravan equipped with API for creating bus protocols in Chisel with ease.

🚀 A platform to inspect GitHub's followers/unfollowers with visualizations and stats.

Amba interconnect library

Open source generator for creating customisable bus topologies (Point-to-point, Shared Bus, CrossBar Switch) based on the bus protocol type provided by the user (AHB, Wishbone, TileLink)

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)