Spike, a RISC-V ISA Simulator

RISC-V Directed Test Framework and Compliance Suite, RiESCUE

GPT-Prompt-Hub is an open-source community-driven repository dedicated to the collection, sharing, and refinement of custom GPT prompts

Explore and share high-quality ChatGPT prompt words. 🌟 Innovate content to enhance the conversation experience and inspire creativity. ✨ Welcome to provide unique tips. 探索和分享高质量的ChatGPT提示词。📚 创新内容，增…

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU G…

A very simple and easy to understand RISC-V core.

PSSGen: Portable Test and Stimulus Standard DSL Generator

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

本文原文由知名 Hacker Eric S. Raymond 所撰寫，教你如何正確的提出技術問題並獲得你滿意的答案。

The Ultra-Low Power RISC-V Core

RV64GC Linux Capable RISC-V Core

Archived, please use official SiFive dev/platform

GreenWaves Technologies RISC-V GAP: development platform for PlatformIO

This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL) programmes, detect syntax, logic and human errors in codes and rectify them.

Instruction Set Generator initially contributed by Futurewei

Random instruction generator for RISC-V processor verification

RISC-V CPU Core (RV32IM)

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

Duolingo web app clone written with React, TypeScript, Next.js, Tailwind, and Zustand. Initialized with create-t3-app.