The following code snippet parses the bench file "network.bench" and calls the methods on_input and on_gate for each input and gate declaration in the file, respectively.
#include <lorina/lorina.hpp>
class reader : public bench_reader
{
public:
void on_input( const std::string& name ) const override
{
/* ... */
}
void on_gate( const std::vector<std::string>& inputs, const std::string& output,
const std::string& type ) const override
{
/* ... */
}
}; /* reader */
read_bench( "network.bench", reader() );Besides parsing, the reader supports a mechanism to react on parse errors.
#include <lorina/diagnostics.hpp>
class diagnostics : public diagnostic_engine
{
public:
void emit( diagnostic_level level, const std::string& message ) const override
{
/* ... */
}
}; /* diagnostics */
diagnostics diag;
read_bench( "network.bench", reader(), &diag );lorina is part of the EPFL logic synthesis libraries. The other libraries and several examples on how to use and integrate the libraries can be found in the logic synthesis tool showcase.