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uart_verif
uart_verif PublicThis project's objective is to verify the design of the uart protocol implemented in HDL i.e SV
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spi_vip
spi_vip PublicForked from muneebullashariff/spi_vip
Verification IP for SPI protocol
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gpio_vip
gpio_vip PublicForked from muneebullashariff/gpio_vip
Verification IP for GPIO protocol
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axi4_vip
axi4_vip PublicForked from muneebullashariff/axi4_vip
Verification IP for APB protocol
SystemVerilog
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