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shim: add inflateReset Continous integration #401: Commit 4bf531b pushed by pablodelara
47m 16s master
master
47m 16s
Optimize gf N-vect dot product SVE functions Continous integration #400: Pull request #367 synchronize by AWSjswinney
41m 7s AWSjswinney:jswinney/2025-10-14-sve2-pr
AWSjswinney:jswinney/2025-10-14-sve2-pr
41m 7s
Optimize gf N-vect dot product SVE functions Continous integration #399: Pull request #367 synchronize by AWSjswinney
42m 39s AWSjswinney:jswinney/2025-10-14-sve2-pr
AWSjswinney:jswinney/2025-10-14-sve2-pr
42m 39s
Optimize gf N-vect dot product SVE functions Continous integration #398: Pull request #367 opened by AWSjswinney
Action required AWSjswinney:jswinney/2025-10-14-sve2-pr
AWSjswinney:jswinney/2025-10-14-sve2-pr
Action required
shim: fix EOF exception Continous integration #397: Commit c9076a6 pushed by pablodelara
40m 14s master
master
40m 14s
erasure_code: xgft loading optimization for AVX2 & dispatch opimization Continous integration #396: Pull request #365 synchronize by MaodiMa
47m 15s MaodiMa:master
MaodiMa:master
47m 15s
erasure_code: set vsetvli to default parameter and add space Continous integration #395: Commit e64ed02 pushed by pablodelara
49m 31s master
master
49m 31s
erasure_code: add prefetch and vsetvli optimization Continous integration #394: Pull request #351 synchronize by lvshuo2016
2h 1m 44s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
2h 1m 44s
raid: keep sub and jcc in sequence to enable macrofusion. Continous integration #393: Commit c0a10ca pushed by pablodelara
28m 36s master
master
28m 36s
erasure_code: add prefetch and vsetvli optimization Continous integration #392: Pull request #351 synchronize by lvshuo2016
1h 26m 43s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
1h 26m 43s
erasure_code: add prefetch and vsetvli optimization Continous integration #391: Pull request #351 synchronize by lvshuo2016
52m 14s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
52m 14s
erasure_code: add prefetch and vsetvli optimization Continous integration #390: Pull request #351 synchronize by lvshuo2016
Action required lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
Action required
erasure_code: xgft loading optimization for AVX2 & dispatch opimization Continous integration #389: Pull request #365 opened by MaodiMa
40m 53s MaodiMa:master
MaodiMa:master
40m 53s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #388: Pull request #350 synchronize by yinlenree
53m 32s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
53m 32s
erasure_code: add prefetch and vsetvli optimization Continous integration #387: Pull request #351 synchronize by lvshuo2016
Action required lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
Action required
Keep sub and jcc in sequence to enable macrofusion. Continous integration #385: Pull request #363 synchronize by Shark64
50s Shark64:macrofusion-2
Shark64:macrofusion-2
50s
erasure_code: add prefetch and vsetvli optimization Continous integration #384: Pull request #351 synchronize by lvshuo2016
35m 0s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
35m 0s
shim: update README (#111) Continous integration #381: Commit 09d7b05 pushed by pablodelara
29m 11s master
master
29m 11s
erasure_code: add prefetch and vsetvli optimization Continous integration #380: Pull request #351 synchronize by lvshuo2016
54m 35s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
54m 35s
aarch64: Use NEON when SVE width is 128 bits Continous integration #379: Commit aedcd37 pushed by pablodelara
48m 3s master
master
48m 3s
Keep sub and jcc in sequence to enable macrofusion. Continous integration #378: Pull request #363 opened by Shark64
47m 35s Shark64:macrofusion-2
Shark64:macrofusion-2
47m 35s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #377: Pull request #350 synchronize by yinlenree
43m 6s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
43m 6s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #376: Pull request #350 synchronize by yinlenree
42m 20s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
42m 20s
crc: Add vector-accelerated assembly code for RISC-V 64-bit architecture with Zvbc instruction set Continous integration #375: Pull request #350 synchronize by yinlenree
56m 20s zte-riscv:add-crc-riscv-vector-support
zte-riscv:add-crc-riscv-vector-support
56m 20s
erasure_code: add prefetch and vsetvli optimization Continous integration #374: Pull request #351 synchronize by lvshuo2016
47m 42s lvshuo2016:riscv-optimize
lvshuo2016:riscv-optimize
47m 42s