A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.

Reads a state transition system and performs property checking

Python-based Hardware Design Processing Toolkit for Verilog HDL

Pono: A flexible and extensible SMT-based model checker

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)

egg is a flexible, high-performance e-graph library

Solving Boolean Equations based on Action Group Representation Programming and Probability Field

An advanced SAT solver

C++ logic network library

A Parallel SAT Solver with GPU Accelerated Inprocessing

An advanced circuit-based sat solver

A Python API for the MiniSat and MiniCard constraint solvers.

NeuroSAT: Learning a SAT Solver from Single-Bit Supervision

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

EPFL logic synthesis benchmarks

A LaTeX Template for CUHK Thesis

CaDiCaL BackBone Analyzer

Benchmarking end-to-end SAT solvers.

A logic synthesis tool

Implementation of local search-based algorithms for solving SAT and Max-SAT in Python

Solvers used in "Deep cooperation of CDCL and local search for SAT" (SAT best paper) and "Better decision heuristics in CDCL through local search and target phases" (JAIR)

Multi-platform nightly builds of open source digital design and verification tools

Simple Theorem Prover, an efficient SMT solver for bitvectors

Generation of SMT2-LIB proofs from parsing netlists