Bus bridges and other odds and ends

a maximal-length polynomial generator for linear feedback shift registers

PCRE2 development is based here.

The implementation of RISC-V Advanced Interrupt Architecture

Test suite designed to check compliance with the SystemVerilog standard.

RSD: RISC-V Out-of-Order Superscalar Processor

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

A SystemVerilog source file pickler.

Determines the modules declared and instantiated in a SystemVerilog file

SystemVerilog language server

SystemVerilog parser library fully compliant with IEEE 1800-2017

SystemVerilog linter

Championship Value Prediction (CVP) simulator.

This tool lets you search your gadgets on your binaries to facilitate your ROP exploitation. ROPgadget supports ELF, PE and Mach-O format on x86, x64, ARM, ARM64, PowerPC, SPARC, MIPS, RISC-V 64, a…

VRoom! RISC-V CPU

VeeR EL2 Core

JavaSMT - Unified Java API for SMT solvers.

Verification framework and tool for higher-order Scala programs

Symbolic-execution-based verifier for the Viper intermediate verification language.

CVC4 is an efficient open-source automatic theorem prover for satisfiability modulo theories (SMT) problems.

SystemVerilog compiler and language services

Contains the code examples from The UVM Primer Book sorted by chapters.

A Proof-oriented Programming Language

TurnKey artifact for Z3

DSL in Scala for Constraint Solving with Z3 SMT Solver

Supporting code for the tutorials on https://www.baeldung.com/scala

Bao, a Lightweight Static Partitioning Hypervisor

Java Constraint Programming solver

An open-source Java library for Constraint Programming