10-stage out-of-order RV64IMAFDC CPU

Digital Design with Chisel

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Light-weight system monitor for X, Wayland, and other things, too

Open source process design kit for 28nm open process

Floating point code in System Verilog

rfPhoenix CPU / GPGPU core

Online demonstration for DigitalJS

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Library for conversion of HWT hardware representation to graph formats for visualization purposes

Implements a version of the parallel random-access machine used in theoretical computer science courses with a memory sharing model based on a binary tree of processor cores.

A reconfigurable logic circuit made of identical rotatable tiles.

This repository contains SRAm based TCAM (ternary content addrerssable memory) IP.

BOOM's Simulation Accelerator.

Synchronous FIFOs designed in Verilog/System Verilog.

UCC Computer Science CK401 Lecture notes

VRoom! RISC-V CPU

Convert dot files to Verilog netlist for Dynamatic

💻 Simple DiVinE custom ISA processing unit

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

Scratch Blocks is a library for building creative computing interfaces.

Virtual Machine used to represent, run, and maintain the state of programs for Scratch 3.0

Graphical User Interface for creating and running Scratch 3.0 projects.

Synthesisable SIMT-style RISC-V GPGPU

Telosys generator based on Velocity template engine

SILVER - Statistical Independence and Leakage Verification

Skill language interpreter

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications