my trivial CPU
- chap4: pipeline supports
ORI; - chap5: support
and, or, xor, etc..., and their Data Hazard; - chap6: add
hilo_reg.vmodule, supportmov, mfhi, mthi, etc..., and their Data Hazard; - chap7: add
arithmeticinst andmul,divinst; - chap8:
jumpandbranchinst, and Branch Hazard; - chap9:
loadandstoreinst,