jjkt · jjkt · Feb 8, 2025 · Jan 25, 2025 · Feb 8, 2025
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/src/trace.rs b/src/trace.rs
@@ -17,6 +17,7 @@ pub fn format_trace_entry(processor: &Processor, symboltable: &HashMap<u32, &str
     let opcode_str = match thumb {
         ThumbCode::Thumb32 { opcode } => format!("{:08X}", opcode).with_exact_width(8),
         ThumbCode::Thumb16 { opcode } => format!("{:04X}", opcode).with_exact_width(8),
+        ThumbCode::Undefined => format!("undef").with_exact_width(8),
     };
 
     let instruction_str = format!("{}", instruction).with_exact_width(32);

diff --git a/testall.sh b/testall.sh
@@ -30,8 +30,7 @@ echo "building..."
 ##
 ## ARM CMSIS DSP
 ##
-# TODO: enable once basic level VFP support is done
-# ./test_arm-cmsis-dsp.sh
+./test_arm-cmsis-dsp.sh
 
 ##
 ## TODO: Rusty Clock

diff --git a/tests/cmsis/Makefile b/tests/cmsis/Makefile
@@ -19,7 +19,7 @@ CFLAGS_LIB := -Wsign-compare \
  -Wall -Wextra -Werror \
  -fshort-enums
 
-CFLAGS= -DSEMIHOSTING -ffunction-sections -mfp16-format=ieee -fdata-sections -std=c11 -Ofast -ffast-math -flax-vector-conversions -DDISABLEFLOAT16  --specs=rdimon.specs --specs=nano.specs -mthumb -Wl,--gc-sections -g -nostartfiles -T link.ld -D__STARTUP_CLEAR_BSS
+CFLAGS= -DSEMIHOSTING -ffunction-sections -mfp16-format=ieee -fdata-sections -std=c11 -Ofast -ffast-math -flax-vector-conversions -DDISABLEFLOAT16  --specs=rdimon.specs -u _printf_float -mthumb -Wl,--gc-sections -g -nostartfiles -T link.ld -D__STARTUP_CLEAR_BSS
 
 # libraries to link
 LIBS=-lCMSISDSP-$(TARGET) -lc -lrdimon -lm

diff --git a/tests/instruction-test-bench/main.c b/tests/instruction-test-bench/main.c
@@ -1,6 +1,7 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <assert.h>
+#include <stdint.h>
 
 /*
 This test bench is used to test various ARM Cortex-M instructions.
@@ -152,10 +153,53 @@ double vsub_f64(double a, double b)
 }
 #endif
 
+int32_t vcvt_f32_s32(float a)
+{
+    return (int32_t)a;
+}
+
+uint32_t vcvt_f32_u32(float a)
+{
+    return (uint32_t)a;
+}
+
+float vcvt_s32_f32(int32_t a)
+{
+    return (float)a;
+}
+
+float vcvt_u32_f32(uint32_t a)
+{
+    return (float)a;
+}
+
+
+#if HARD_FLOATING_POINT_DOUBLE_PRECISION
+int32_t vcvt_f64_s32(double a)
+{
+    return (int32_t)a;
+}
+uint32_t vcvt_f64_u32(double a)
+{
+    return (uint32_t)a;
+}
+
+double vcvt_s32_f64(int32_t a)
+{
+    return (double)a;
+}
+
+double vcvt_u32_f64(uint32_t a)
+{
+    return (double)a;
+}
+
+#endif
+
 void floating_point(void)
 {
     // Try to generate floating-point data-processing instructions
-    // TODO: VCVT, VDIV, VFMA, VFNMA, VMAXNM
+    // TODO: VDIV, VFMA, VFNMA, VMAXNM
     // VMLA, VMOV, VMOV, VMUL, VNEG, VNMLA, VRINTA, VRINTZ
     // VSEL, VSQRT
 
@@ -192,6 +236,34 @@ void floating_point(void)
     assert(vsub_f64(-1.0, 2.0) == (-1.0 - 2.0));
     assert(vsub_f64(-1.0, -2.0) == (-1.0 - -2.0));
 #endif
+
+    // floating point to integer conversion
+
+    assert(vcvt_f32_s32(42.0f) == 42);
+    assert(vcvt_f32_s32(-42.0f) == -42);
+    assert(vcvt_f32_u32(42.0f) == 42);
+    assert(vcvt_f32_u32(-42.0f) == 0);
+
+    // integer to floating point conversion
+    assert(vcvt_s32_f32(42) == 42.0f);
+    assert(vcvt_s32_f32(-42) == -42.0f);
+    assert(vcvt_u32_f32(42) == 42.0f);
+    assert(vcvt_u32_f32(0) == 0.0f);
+
+
+#if HARD_FLOATING_POINT_DOUBLE_PRECISION
+    assert(vcvt_f64_s32(42.0) == 42);
+    assert(vcvt_f64_s32(-42.0) == -42);
+    assert(vcvt_f64_u32(42.0) == 42);
+    assert(vcvt_f64_u32(-42.0) == 0);
+
+    // integer to floating point conversion
+    assert(vcvt_s32_f64(42) == 42.0);
+    assert(vcvt_s32_f64(-42) == -42.0);
+    assert(vcvt_u32_f64(42) == 42.0);
+    assert(vcvt_u32_f64(0) == 0.0);
+#endif
+
 }
 #endif
 int main(void)

diff --git a/tests/rules.mk b/tests/rules.mk
@@ -5,7 +5,7 @@ ifndef GCC_HOME
 endif
 
 CC=$(GCC_HOME)/bin/arm-none-eabi-gcc
-CFLAGS= -O2 --specs=rdimon.specs -mthumb -g -nostartfiles -T link.ld -D__STARTUP_CLEAR_BSS
+CFLAGS= -O2 --specs=rdimon.specs -u _printf_float -mthumb -g -nostartfiles -T link.ld -D__STARTUP_CLEAR_BSS
 LIBS=-lc -lrdimon
 
 # check the expected dir for the startup file

diff --git a/zmu_cortex_m/Cargo.toml b/zmu_cortex_m/Cargo.toml
@@ -6,6 +6,7 @@ edition = "2021"
 
 [dependencies]
 byteorder = "1"
+enum-as-inner = "0.6.1"
 enum-set = "0.0.8"
 gdbstub = "0.7"
 gdbstub_arch = "0.3"

diff --git a/zmu_cortex_m/build.rs b/zmu_cortex_m/build.rs
@@ -278,7 +278,7 @@ fn main() -> Result<(), Box<dyn Error>> {
         ("111011100.11........101..1.0....", "VSUB_t1"),
         ("111011101.110100....101..1.0....", "VCMP_t1"),
         ("111011101.110101....101..1.0....", "VCMP_t2"),
-        //("111111101.1111......101..1.0....": "VCVT_t1"),
+        ("111011101.111.......101..1.0....", "VCVT_t1"),
         //("111011101.111.1.....101..1.0....": "VCVT_fx_t1"),
         //("111011101.110111....101.11.0....": "VCVT_ds_t1"),
         //("111011101.11001.....101..1.0....": "VCVTB"),

diff --git a/zmu_cortex_m/src/core/bits.rs b/zmu_cortex_m/src/core/bits.rs
@@ -131,6 +131,62 @@ impl Bits for u8 {
     }
 }
 
+impl Bits for i128 {
+    #[inline(always)]
+    fn get_bits(&self, range: Range<usize>) -> Self {
+        let bits = *self << (128 - range.end) >> (128 - range.end);
+        bits >> range.start
+    }
+
+    #[inline(always)]
+    fn get_bit(&self, bit: usize) -> bool {
+        (*self & 1 << bit) == 1 << bit
+    }
+
+    #[inline(always)]
+    fn set_bits(&mut self, range: Range<usize>, value: Self) {
+        let mask: Self = !(((1 << (range.end - range.start)) - 1) << range.start);
+
+        *self &= mask;
+        *self |= value << range.start;
+
+    }
+    #[inline(always)]
+    fn set_bit(&mut self, bit: usize, value: bool) {
+        *self &= !0 ^ (1 << bit);
+        *self |= Self::from(value) << bit;
+    }
+}
+
+impl Bits for u128 {
+    #[inline(always)]
+    fn get_bits(&self, range: Range<usize>) -> Self {
+        let bits = *self << (128 - range.end) >> (128 - range.end);
+        bits >> range.start
+    }
+
+    #[inline(always)]
+    fn get_bit(&self, bit: usize) -> bool {
+        (*self & 1 << bit) == 1 << bit
+    }
+
+    #[inline(always)]
+    fn set_bits(&mut self, range: Range<usize>, value: Self) {
+        let mask: Self = !(((1 << (range.end - range.start)) - 1) << range.start);
+
+        *self &= mask;
+        *self |= value << range.start;
+
+    }
+    #[inline(always)]
+    fn set_bit(&mut self, bit: usize, value: bool) {
+        *self &= !0 ^ (1 << bit);
+        *self |= Self::from(value) << bit;
+    }
+}
+
+
+
 #[cfg(test)]
 mod tests {
 

diff --git a/zmu_cortex_m/src/core/fetch.rs b/zmu_cortex_m/src/core/fetch.rs
@@ -14,6 +14,11 @@ pub trait Fetch {
     /// Fetch instruction from current PC (Program Counter) position,
     /// decoding the possible thumb32 variant
     fn fetch(&self, pc: u32) -> Result<ThumbCode, Fault>;
+
+    /// Fetch instruction from current PC (Program Counter) position,
+    /// decoding the possible thumb32 variant. Do not fail on
+    /// out of bounds access, just return undefined instruction.
+    fn fetch_non_fail(&self, pc: u32) -> ThumbCode;
 }
 
 impl Fetch for Processor {
@@ -32,4 +37,23 @@ impl Fetch for Processor {
             Ok(ThumbCode::Thumb16 { opcode: hw })
         }
     }
+
+    fn fetch_non_fail(&self, pc: u32) -> ThumbCode {
+        match self.read16(pc) {
+            Ok(hw) => {
+                if is_thumb32(hw) {
+                    if let Ok(hw2) = self.read16(pc + 2) {
+                        ThumbCode::Thumb32 {
+                            opcode: (u32::from(hw) << 16) + u32::from(hw2),
+                        }
+                    } else {
+                        ThumbCode::Undefined
+                    }
+                } else {
+                    ThumbCode::Thumb16 { opcode: hw }
+                }
+            }
+            Err(_) => ThumbCode::Undefined,
+        }
+    }
 }